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27 条记录 (耗时 0.022 秒)

    Fin Deformation Modulation
    12.
    发明申请
    Fin Deformation Modulation 审中-公开

    公开(公告)号：US20160163700A1

    公开(公告)日：2016-06-09

    申请号：US15042414

    申请日：2016-02-12

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chih-Tang Peng ,  Tai-Chun Huang ,  Hao-Ming Lien

    IPC分类号： H01L27/088 ,  H01L27/02 ,  H01L29/06

    CPC分类号： H01L27/0886 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/785

    摘要： A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.

    Fin deformation modulation
    13.
    发明授权
    Fin deformation modulation 有权
    翅片变形调制

    公开(公告)号：US09276062B2

    公开(公告)日：2016-03-01

    申请号：US14504149

    申请日：2014-10-01

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chih-Tang Peng ,  Tai-Chun Huang ,  Hao-Ming Lien

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/84 ,  H01L27/088

    CPC分类号： H01L27/0886 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/785

    摘要： A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.

    摘要翻译： 一种方法包括形成从半导体衬底的顶表面延伸到半导体衬底中的多个沟槽，其中半导体条形成在多个沟槽之间。 多个沟槽包括比第一沟槽宽的第一沟槽和第二沟槽。 第一介电材料填充在多个沟槽中，其中第一沟槽基本上完全填充，并且第二沟槽被部分填充。 在第一电介质材料上形成第二电介质材料。 第二介电材料填充第二沟槽的上部，并且具有与第一电介质材料的第一收缩率不同的收缩率。 执行平面化以去除多余的第二电介质材料。 第一介电材料和第二介电材料的剩余部分分别在第一和第二沟槽中形成第一和第二STI区。

    Isolation region gap fill method
    14.
    发明授权
    Isolation region gap fill method 有权
    隔离区间隙填充法

    公开(公告)号：US09177955B2

    公开(公告)日：2015-11-03

    申请号：US13790923

    申请日：2013-03-08

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chih-Tang Peng ,  Tai-Chung Huang ,  Hao-Ming Lien ,  Tze-Liang Lee

    IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/108 ,  H01L21/762 ,  H01L21/8234

    CPC分类号： H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/10879 ,  H01L29/7831

    摘要： An isolation region gap fill method comprises depositing a first dielectric material over a semiconductor device through a flowable deposition process or other gap fill deposition processes, wherein the semiconductor device includes a first FinFET comprising a plurality of first fins and a second FinFET comprising a plurality of second fins. The method further comprises removing the first dielectric material between the first FinFET and the second FinFET to form an inter-device gap, depositing a second dielectric material into the inter-device gap and applying an annealing process to the semiconductor device.

    摘要翻译： 隔离区间隙填充方法包括通过可流动沉积工艺或其它间隙填充沉积工艺在半导体器件上沉积第一介电材料，其中半导体器件包括包括多个第一鳍片的第一FinFET和包括多个第一鳍片 第二个鳍。 该方法还包括去除第一FinFET和第二FinFET之间的第一介电材料以形成器件间间隙，将第二介电材料沉积到器件间间隙中，并向半导体器件施加退火工艺。

    Injector for forming films respectively on a stack of wafers
    17.
    发明授权
    Injector for forming films respectively on a stack of wafers 有权
    注射器用于分别在一叠晶片上形成薄膜

    公开(公告)号：US09017763B2

    公开(公告)日：2015-04-28

    申请号：US13716052

    申请日：2012-12-14

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Wei-Che Hsieh ,  Brian Wang ,  Tze-Liang Lee ,  Yi-Hung Lin ,  Hao-Ming Lien ,  Shiang-Rung Tsai ,  Tai-Chun Huang

    IPC分类号： B05B1/14 ,  H01L21/00

    CPC分类号： C23C16/45578 ,  C23C16/45504 ,  C23C16/45546 ,  C23C16/4584 ,  C23C16/52 ,  C23C16/54 ,  H01L21/00

    摘要： An injector for forming films respectively on a stack of wafers is provided. The injector includes a plurality of hole structures. Every adjacent two of the wafers have therebetween a wafer spacing, and each of the wafers has a working surface. The hole structures respectively correspond to the respective wafer spacings. The working surface and a respective hole structure have therebetween a parallel distance. The parallel distance is larger than a half of the wafer spacing. A wafer processing apparatus and a method for forming films respectively on a stack of wafers are also provided.

    摘要翻译： 提供了分别在一叠晶片上形成薄膜的注射器。 喷射器包括多个孔结构。 每个相邻的两个晶片之间具有晶片间隔，并且每个晶片具有工作表面。 孔结构分别对应于相应的晶片间隔。 工作表面和相应的孔结构之间具有平行的距离。 平行距离大于晶片间距的一半。 还提供了晶片处理装置和分别在晶片叠层上形成薄膜的方法。

    Strained Isolation Regions
    18.
    发明申请
    Strained Isolation Regions 审中-公开
    应变隔离区域

    公开(公告)号：US20140242776A1

    公开(公告)日：2014-08-28

    申请号：US14258832

    申请日：2014-04-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Mong-Song Liang ,  Tze-Liang Lee ,  Kuo-Tai Huang ,  Chao-Cheng Chen ,  Hao-Ming Lien ,  Chih-Tang Peng

    IPC分类号： H01L29/10 ,  H01L29/78

    CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846

    摘要： A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.

    摘要翻译： 提供了形成具有局部应力源的隔离沟槽的方法。 根据本发明的实施例，在衬底中形成沟槽并且部分地填充有电介质材料。 在一个实施例中，沟槽被填充有电介质层，并且执行平面化步骤以使其与衬底的表面平坦化。 然后将电介质材料凹入到衬底的表面下方。 在沟槽的凹陷部分中，电介质材料可以沿着侧壁保留，或者电介质材料可以沿侧壁去除。 然后可以在凹陷部分内的电介质材料上形成拉伸或压缩的应力膜。 应力膜也可以在晶体管或其它半导体结构上延伸。

    Fin deformation modulation
    19.
    发明授权
    Fin deformation modulation 有权

    公开(公告)号：US10103141B2

    公开(公告)日：2018-10-16

    申请号：US15042414

    申请日：2016-02-12

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chih-Tang Peng ,  Tai-Chun Huang ,  Hao-Ming Lien

    IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L21/84 ,  H01L27/02

    摘要： A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.