公开(公告)号：US09502358B2

公开(公告)日：2016-11-22

申请号：US14332986

申请日：2014-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chung-Hui Chen

IPC: H01L29/40 ,  H01L23/552 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L23/552 ,  H01L23/5225 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a signal line and a plurality of shielding structures. The signal line is routed along a first direction and is in a first metallization layer. Each shielding structure includes a plurality of non-contiguous shielding patterns aligned along the first direction. The plurality of shielding structures includes a first and a second shielding structures in a second metallization layer that adjoins the first metallization layer and a third and a fourth shielding structures in a third metallization layer that adjoins the first metallization layer. The first metallization layer is between the second and the third metallization layers. The first and the second shielding structures are separated from each other along a second direction perpendicular to the first direction. The third and the fourth shielding structures are separated from each other along the second direction.

Abstract translation: 集成电路包括信号线和多个屏蔽结构。 信号线沿着第一方向布线并且处于第一金属化层中。 每个屏蔽结构包括沿着第一方向排列的多个不连续的屏蔽图案。 多个屏蔽结构包括邻接第一金属化层的第二金属化层中的第一和第二屏蔽结构以及邻接第一金属化层的第三金属化层中的第三和第四屏蔽结构。 第一金属化层位于第二和第三金属化层之间。 第一和第二屏蔽结构沿垂直于第一方向的第二方向彼此分离。 第三和第四屏蔽结构沿第二方向彼此分离。

公开(公告)号：US09141754B2

公开(公告)日：2015-09-22

申请号：US14489155

申请日：2014-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chien-Hung Chen ,  Yung-Chow Peng ,  Chung-Hui Chen ,  Chih-Ming Yang

IPC: G06F17/50 ,  H01L27/02 ,  H01L29/94

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/08 ,  G06F2217/12 ,  H01L27/0207 ,  H01L29/94

Abstract: A method comprises generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also comprises generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further comprises selecting a layout generation configuration for generating the layout of semiconductor components. The method additionally comprises generating the layout of semiconductor components based on the selected layout generation configuration.

Abstract translation: 一种方法包括生成半导体部件布局的第一组配置。 第一组配置的配置各自满足一组设计规则的第一子集。 该方法还包括生成半导体部件布局的第二组配置。 第二组配置是通过消除第一组配置的一个或多个配置而基于确定所述第一组配置的消除的一个或多个配置不能满足该组设计规则的第二子集来生成的 。 该方法还包括选择用于生成半导体部件的布局的布局生成配置。 该方法还包括基于所选择的布局生成配置来生成半导体部件的布局。

公开(公告)号：US12094872B2

公开(公告)日：2024-09-17

申请号：US17643651

申请日：2021-12-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hui Chen ,  Wan-Te Chen ,  Shu-Wei Chung ,  Tung-Heng Hsieh ,  Tzu-Ching Chang ,  Tsung-Hsin Yu ,  Yung Feng Chang

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/0629 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate. A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first and second nanosheet structures have at least one nanosheet forming source/drain regions and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first and second nanosheet structures. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure and the gate structure of the first nanosheet structure define a capacitor.

公开(公告)号：US12068306B2

公开(公告)日：2024-08-20

申请号：US18312219

申请日：2023-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chung-Hui Chen ,  Tzu-Ching Chang ,  Cheng-Hsiang Hsieh

IPC: H01L27/02 ,  G06F30/3953 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/0207 ,  G06F30/3953 ,  H01L23/5226 ,  H01L23/528

Abstract: An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first transistor and a second transistor over the first side of the substrate, a first conductive pattern over the first side of the substrate, and a second conductive pattern under the second side of the substrate. The first conductive pattern electrically couples a first terminal of the first transistor to a second terminal of the second transistor. The second conductive pattern electrically couples the first terminal of the first transistor to the second terminal of the second transistor.

公开(公告)号：US11676957B2

公开(公告)日：2023-06-13

申请号：US17189908

申请日：2021-03-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chung-Hui Chen ,  Tzu-Ching Chang ,  Cheng-Hsiang Hsieh

IPC: H01L27/02 ,  G06F30/3953 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/0207 ,  G06F30/3953 ,  H01L23/528 ,  H01L23/5226

Abstract: An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first conductive pattern over the active region, and a second conductive pattern under the second side of the substrate. The active region includes a first portion and a second portion. The first conductive pattern is electrically coupled to the first portion and the second portion of the active region. The second conductive pattern is electrically coupled to the first portion and the second portion of the active region.

公开(公告)号：US11562953B2

公开(公告)日：2023-01-24

申请号：US16660363

申请日：2019-10-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chung-Hui Chen ,  Hao-Chieh Chan

IPC: H01L23/528 ,  H01L23/50 ,  H01L23/522 ,  G06F30/39 ,  H01L21/8238

Abstract: An integrated circuit includes two parallel active zones extending in a first direction, an n-type pick-up region, and a p-type pick-up region. The two parallel active zones includes a p-type active zone located in an n-type well and an n-type active zone located in a p-type well. The n-type pick-up region is located in the n-type well and configured to have a first supply voltage. The p-type pick-up region is located in the p-type well and configured to have a second supply voltage, wherein the second supply voltage is lower than the first supply voltage. The n-type pick-up region and the p-type pick-up region are separated from each other along a direction that is different from the first direction.

公开(公告)号：US11494542B2

公开(公告)日：2022-11-08

申请号：US16741440

申请日：2020-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chung-Hui Chen ,  Tzu Ching Chang ,  Wan-Te Chen

IPC: G06F30/392 ,  H01L23/522 ,  G03F1/70 ,  G06F30/3953 ,  G06F30/398

Abstract: A semiconductor device includes: an active area in a transistor layer; contact-source/drain (CSD) conductors in the transistor layer; gate conductors in the transistor layer, and interleaved with the CSD conductors; VG structures in the transistor layer, and over the active area; and a first gate-signal-carrying (GSC) conductor in an M_1st layer that is over the transistor layer, and that is over the active area; and wherein long axes correspondingly of the active area and the first GSC conductor extend substantially in a first direction; and long axes correspondingly of the CSD conductors and the gate conductors extend substantially in a second direction, the second direction being substantially perpendicular to the first direction.

公开(公告)号：US10720361B2

公开(公告)日：2020-07-21

申请号：US16512041

申请日：2019-07-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

IPC: H01L27/07 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02 ,  H01L29/94 ,  H01L29/40

Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

公开(公告)号：US10510826B2

公开(公告)日：2019-12-17

申请号：US15966406

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Chieh Chan ,  Chung-Hui Chen

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L27/08 ,  H01L27/06 ,  H01L29/94 ,  H01L27/02

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

公开(公告)号：US09354124B2

公开(公告)日：2016-05-31

申请号：US14193563

申请日：2014-02-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jaw-Juinn Horng ,  Szu-Lin Liu ,  Chung-Hui Chen

IPC: H03K5/153 ,  G01K7/01 ,  G01R19/00

CPC classification number: G01K7/01 ,  G01R19/0084

Abstract: A circuit includes a comparator unit, a capacitive device, and a switching network. The comparator unit is configured to set a control signal at a first logical value when an output voltage reaches a first voltage value from being less than the first voltage value, and to set the control signal at a second logical value when the output voltage reaches a second voltage value from being greater than the second voltage. The capacitive device provides the output voltage. The switching network is configured to charge or discharge the capacitive device based on the control signal.

Abstract translation: 电路包括比较器单元，电容器件和开关网络。 比较器单元被配置为当输出电压达到小于第一电压值的第一电压值时，将控制信号设置在第一逻辑值，并且当输出电压达到第一逻辑值时将控制信号设置在第二逻辑值 第二电压值大于第二电压。 电容器件提供输出电压。 交换网络被配置为基于控制信号对电容性设备进行充电或放电。