公开(公告)号：US11562953B2

公开(公告)日：2023-01-24

申请号：US16660363

申请日：2019-10-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chung-Hui Chen ,  Hao-Chieh Chan

IPC: H01L23/528 ,  H01L23/50 ,  H01L23/522 ,  G06F30/39 ,  H01L21/8238

Abstract: An integrated circuit includes two parallel active zones extending in a first direction, an n-type pick-up region, and a p-type pick-up region. The two parallel active zones includes a p-type active zone located in an n-type well and an n-type active zone located in a p-type well. The n-type pick-up region is located in the n-type well and configured to have a first supply voltage. The p-type pick-up region is located in the p-type well and configured to have a second supply voltage, wherein the second supply voltage is lower than the first supply voltage. The n-type pick-up region and the p-type pick-up region are separated from each other along a direction that is different from the first direction.

公开(公告)号：US10510826B2

公开(公告)日：2019-12-17

申请号：US15966406

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Chieh Chan ,  Chung-Hui Chen

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L27/08 ,  H01L27/06 ,  H01L29/94 ,  H01L27/02

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

公开(公告)号：US12125781B2

公开(公告)日：2024-10-22

申请号：US17871213

申请日：2022-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chung-Hui Chen ,  Hao-Chieh Chan

IPC: H01L27/02 ,  G06F30/39 ,  H01L21/8238 ,  H01L23/50 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/50 ,  G06F30/39 ,  H01L21/823892 ,  H01L23/5226 ,  H01L23/5286

Abstract: A method of forming a semiconductor device. The method includes forming a first well of a first-type in a substrate of a second-type, forming a first active zone of the first-type in a second well of the second-type on the substrate, and forming a second active zone of the second-type in the first-type well. The method also includes forming a first pick-up region of the first-type located in the first well, and forming a second pick-up region of the second-type located in the second well. Each of the first active zone and the second active zone extends in a first direction. The first pick-up region and the second pick-up region are separated from each other, by the first active zone and the second active zone, along a direction that is different from the first direction.

公开(公告)号：US11289569B2

公开(公告)日：2022-03-29

申请号：US16709464

申请日：2019-12-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Chieh Chan ,  Chung-Hui Chen

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L27/08 ,  H01L27/06 ,  H01L29/94 ,  H01L27/02

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

公开(公告)号：US20190006458A1

公开(公告)日：2019-01-03

申请号：US15966406

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Chieh Chan ,  Chung-Hui Chen

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L27/08 ,  H01L21/762

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

公开(公告)号：US09865550B2

公开(公告)日：2018-01-09

申请号：US14086100

申请日：2013-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hao-Chieh Chan

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  G06F1/32 ,  H01L25/065 ,  H01L25/18 ,  H01L23/48

CPC classification number: H01L23/5386 ,  G06F1/32 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/37001

Abstract: A pattern generator includes and upper chip and one or more lower chips. The upper chip includes an upper substrate and a plurality of conductive plates on the upper substrate. The plurality of conductive plates is arranged as an array. The one or more lower chips include one or more lower substrates and a plurality of driving circuits each on one of the one or more lower substrates and electrically coupled with a corresponding one of the plurality of conductive plates. The upper chip and the one or more lower chips are stacked one over another.

公开(公告)号：US09436196B2

公开(公告)日：2016-09-06

申请号：US14464214

申请日：2014-08-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hao-Chieh Chan

IPC: G05F1/56 ,  G05F1/618 ,  G05F1/613

CPC classification number: G05F1/56 ,  G05F1/613 ,  G05F1/618

Abstract: A device includes a voltage buffer, a load compensation circuit, and a closed-loop current feedback circuit. The voltage buffer is configured to output an output voltage and an output current. The output current is the sum of a load current and a bias current. The load compensation circuit is configured to output the bias current at a variable level based on a variation in the load current. The closed-loop current feedback circuit is configured to feedback a voltage level based on the variation to the load compensation circuit.

Abstract translation: 一种装置包括电压缓冲器，负载补偿电路和闭环电流反馈电路。 电压缓冲器被配置为输出输出电压和输出电流。 输出电流是负载电流和偏置电流的总和。 负载补偿电路被配置为基于负载电流的变化将偏置电流输出为可变电平。 闭环电流反馈电路被配置为基于对负载补偿电路的变化来反馈电压电平。