公开(公告)号：US20190355727A1

公开(公告)日：2019-11-21

申请号：US16242127

申请日：2019-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Keunnam Kim ,  Eun A Kim ,  Eunjung Kim ,  Jeongseop Shim

IPC: H01L27/108 ,  H01L27/22 ,  H01L27/24 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L29/423

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises forming an active structure including a plurality of active patterns, a device isolation layer defining the active patterns, and a gate structure across the active patterns and extending in a first direction, forming a first mask pattern on the active structure, and forming a trench by using the first mask pattern as an etching mask to pattern the active structure. Forming the first mask pattern comprises forming in a first mask layer a plurality of first openings extending in a second direction intersecting the first direction, and forming in the first mask layer a plurality of second openings extending in a third direction intersecting the first and second directions.

公开(公告)号：US10332890B2

公开(公告)日：2019-06-25

申请号：US15653198

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Chan-Sic Yoon ,  Augustin Hong ,  Keunnam Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Jemin Park ,  Hoin Lee ,  Sungho Jang ,  Kiwook Jung ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/24 ,  H01L27/22

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US12302551B2

公开(公告)日：2025-05-13

申请号：US17745960

申请日：2022-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Keunnam Kim

IPC: H10B12/00

Abstract: A semiconductor memory device including a stack including layer groups vertically stacked on a substrate, each of the layer groups including a word line, a lower channel layer, an upper channel layer, and a data storing element electrically connected to the lower channel layer and the upper channel layer; and a bit line at a side of the stack, the bit line extending vertically, wherein the bit line includes a protruding portion connected to the lower channel layer and the upper channel layer of each layer group, the word line of each layer group extends in a first direction parallel to a top surface of the substrate, and the word line of each layer group is sandwiched between the lower channel layer and the upper channel layer of the layer group.

公开(公告)号：US12279415B2

公开(公告)日：2025-04-15

申请号：US18337134

申请日：2023-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Choi ,  Myeong-Dong Lee ,  Hyeon-Woo Jang ,  Keunnam Kim ,  Sooho Shin ,  Yoosang Hwang

IPC: H10B12/00 ,  G11C5/12

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

公开(公告)号：US20230389287A1

公开(公告)日：2023-11-30

申请号：US18144885

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byeongjoo Ku ,  Keunnam Kim ,  Kiseok Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor device includes: a substrate including a cell array area, a periphery circuit area, and an interface area; bit lines arranged in the cell array area and extending in a first horizontal direction; a mold insulating layer arranged on the bit lines and including openings extending in a second horizontal direction; channel layers respectively arranged on the bit lines in each of the openings; word lines respectively arranged on the channel layers and extending in the second horizontal direction from the cell array area to the interface area, the word lines including a first word line on a first sidewall of each opening of the mold insulating layer and a second word line on a second sidewall of the opening; and a trimming insulating block arranged in the interface area and connected to an end of the first word line and an end of the second word line.

公开(公告)号：US20230290727A1

公开(公告)日：2023-09-14

申请号：US18321917

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L23/528 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/528 ,  H01L21/76805 ,  H10B12/03 ,  H10B12/34 ,  H10B12/48 ,  H10B12/50 ,  H10B12/315 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/485 ,  H01L21/76807 ,  H10B12/053

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US20220028860A1

公开(公告)日：2022-01-27

申请号：US17192084

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Choi ,  Myeong-Dong Lee ,  Hyeon-Woo Jang ,  Keunnam Kim ,  Sooho Shin ,  Yoosang Hwang

IPC: H01L27/108

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

公开(公告)号：US11101283B2

公开(公告)日：2021-08-24

申请号：US16508839

申请日：2019-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Kiseok Lee ,  Keunnam Kim ,  Yoosang Hwang

IPC: H01L27/11578 ,  H01L27/11573 ,  H01L27/1157

Abstract: A semiconductor device may include a stack structure that includes a plurality of layers vertically stacked on a substrate, and a plurality of gate electrodes that vertically extend to penetrate the stack structure. Each of the plurality of layers may include a plurality of semiconductor patterns that extend in parallel along a first direction, a bit line that is electrically connected to the semiconductor patterns and extends in a second direction intersecting the first direction, a first air gap on the bit line, and a data storage element that is electrically connected to a corresponding one of the semiconductor patterns. The first air gap is interposed between the bit line of a first layer of the plurality of layers and the bit line of a second layer of the plurality of layers.

公开(公告)号：US11100958B2

公开(公告)日：2021-08-24

申请号：US16522958

申请日：2019-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-Jung Kim ,  Keunnam Kim ,  Hunkook Lee ,  Yoosang Hwang

IPC: H01L27/105 ,  G11C5/06 ,  G11C8/14 ,  G11C7/18

Abstract: A semiconductor memory device comprising a substrate including a cell region, first and second contact regions, and a bit peripheral circuit region disposed between the first and second contact regions. A first stack structure is disposed on the cell region and the first contact region. A second stack structure is disposed on the cell region and the second contact region. A peripheral transistor is disposed on the bit peripheral circuit region and is electrically connected to the first and second stack structures. Each of the first and second stack structures comprises semiconductor patterns vertically stacked on the cell region, and conductive lines having connection with the semiconductor patterns and extending along a first direction from the cell region onto corresponding first and second contact regions. The conductive lines have stepwise structures on the first and second contact regions.

公开(公告)号：US10978397B2

公开(公告)日：2021-04-13

申请号：US16707294

申请日：2019-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L21/764 ,  H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L27/24

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.