公开(公告)号：US20220415801A1

公开(公告)日：2022-12-29

申请号：US17902319

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonjin SHIN ,  Minhyun LEE ,  Changseok LEE ,  Hyeonsuk SHIN ,  Seokmo HONG

IPC: H01L23/532 ,  H01L23/522

Abstract: An interconnect structure and an electronic apparatus including the interconnect structure are provided. The interconnect structure includes a conductive layer; a dielectric layer configured to surround at least a part of the conductive layer; and a diffusion barrier layer disposed between the conductive layer and the dielectric layer and configured to limit and/or prevent a conductive material of the conductive layer from diffusing into the dielectric layer, and at least one of the dielectric layer and the diffusion barrier layer includes a boron nitride layer of a low dielectric constant.

公开(公告)号：US20210305378A1

公开(公告)日：2021-09-30

申请号：US17014127

申请日：2020-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Hyeonjin SHIN ,  Minseok YOO ,  Minhyun LEE

IPC: H01L29/41 ,  H01L29/417 ,  H01L29/24 ,  H01L29/06 ,  H01L29/45 ,  H01L29/786 ,  H01L29/66

Abstract: Provided are two-dimensional material (2D)-based wiring conductive layer contact structures, electronic devices including the same, and methods of manufacturing the electronic devices. A 2D material-based field effect transistor includes a substrate; first to third 2D material layers on the substrate; an insulating layer on the first 2D material layer; a source electrode on the second 2D material layer; a drain electrode on the third 2D material layer; and a gate electrode on the insulating layer. The first 2D material layer is configured to exhibit semiconductor characteristics, and the second and third 2D material layers are metallic 2D material layers. The first 2D material layer may include a first channel layer of a 2D material and a second channel layer of a 2D material. The first 2D material layer may partially overlap the second and third 2D material layers.

公开(公告)号：US20210296445A1

公开(公告)日：2021-09-23

申请号：US17203010

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/24

Abstract: A field effect transistor includes a substrate, a source electrode and a drain electrode on the substrate and apart from each other in a first direction, a plurality of channel layers, a gate insulating film surrounding each of the plurality of channel layers, and a gate electrode surrounding the gate insulating film. Each of the plurality of channel layers has ends contacting the source electrode and the drain electrode. The plurality of channel layers are spaced apart from each other in a second direction away from the substrate. The plurality of channel layers include a 2D semiconductor material.

公开(公告)号：US20210288171A1

公开(公告)日：2021-09-16

申请号：US17201485

申请日：2021-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/24 ,  H01L27/092

Abstract: A vertical type transistor includes: a substrate; a first source/drain electrode layer provided on the substrate; a second source/drain electrode layer provided above the first source/drain electrode layer; a first gate electrode layer provided between the first and second source/drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source/drain electrode layer, the first gate insulating film, and the first source/drain electrode layer; and a first channel layer provided on a lateral side of the hole, wherein the first channel layer may include a 2D semiconductor.

公开(公告)号：US20250098171A1

公开(公告)日：2025-03-20

申请号：US18885031

申请日：2024-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghun KIM ,  Hoseok HEO ,  Sunho KIM ,  Seungyeul YANG ,  Minhyun LEE ,  Seokhoon CHOI

IPC: H10B43/30 ,  H10B43/27

Abstract: A memory device includes: a channel layer; a gate electrode spaced apart from the channel layer; and a multilayer charge trap layer disposed between the channel layer and the gate electrode, wherein the multilayer charge trap layer includes silicon oxynitride, the silicon oxynitride including gallium or silicon nitride including gallium.

公开(公告)号：US20240224530A1

公开(公告)日：2024-07-04

申请号：US18215533

申请日：2023-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungdam HYUN ,  Kyunghun KIM ,  Sunho KIM ,  Hyungyung KIM ,  Kwangmin PARK ,  Seungyeul YANG ,  Gukhyon YON ,  Minhyun LEE ,  Seokhoon CHOI ,  Hoseok HEO

IPC: H10B43/35 ,  G11C16/04 ,  H01L29/423 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/27

Abstract: A vertical NAND flash memory device includes a plurality of cell arrays, where each cell array of the plurality of cell arrays includes a channel layer, a charge trap layer provided on the channel layer, the charge trap layer including a matrix comprising a dielectric and a charge trap material in the matrix and including anti-ferroelectric nanocrystals or ferroelectric nanocrystals, and a plurality of gate electrodes provided on the charge trap layer.

公开(公告)号：US20240038903A1

公开(公告)日：2024-02-01

申请号：US18483058

申请日：2023-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Hyeonjin SHIN ,  Minseok YOO ,  Minhyun LEE

IPC: H01L29/786 ,  H01L29/41 ,  H01L29/417 ,  H01L29/24 ,  H01L29/66 ,  H01L29/45 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/16

CPC classification number: H01L29/78696 ,  H01L29/413 ,  H01L29/41733 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/45 ,  H01L29/0665 ,  H01L21/02417 ,  H01L21/02568 ,  H01L21/823412 ,  H01L29/1606

Abstract: Provided are two-dimensional material (2D)-based wiring conductive layer contact structures, electronic devices including the same, and methods of manufacturing the electronic devices. A 2D material-based field effect transistor includes a substrate; first to third 2D material layers on the substrate; an insulating layer on the first 2D material layer; a source electrode on the second 2D material layer; a drain electrode on the third 2D material layer; and a gate electrode on the insulating layer. The first 2D material layer is configured to exhibit semiconductor characteristics, and the second and third 2D material layers are metallic 2D material layers. The first 2D material layer may include a first channel layer of a 2D material and a second channel layer of a 2D material. The first 2D material layer may partially overlap the second and third 2D material layers.

公开(公告)号：US20230395665A1

公开(公告)日：2023-12-07

申请号：US18052017

申请日：2022-11-02

Applicant: Samsung Electronics Co., Ltd. ,  THE UNIVERSITY OF CHICAGO ,  Center for Technology Licensing at Cornell University

Inventor： Minhyun LEE ,  Jiwoong PARK ,  Saien XIE ,  Jinseong HEO ,  Hyeonjin SHIN

IPC: H01L29/15 ,  H01L29/10

CPC classification number: H01L29/158 ,  H01L29/1054

Abstract: Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap.

公开(公告)号：US20220328671A1

公开(公告)日：2022-10-13

申请号：US17539768

申请日：2021-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Hyeonjin SHIN ,  Minhyun LEE ,  Taejin CHOI ,  Sangwon KIM ,  Bongseob YANG ,  Eunkyu LEE

IPC: H01L29/76 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24

Abstract: A field effect transistor structure is disclosed. The field effect transistor structure includes: a fin-shaped channel protruding from a substrate and extending in one direction; a source electrode on one side of the fin-shaped channel; a drain electrode separated from the source electrode with the fin-shaped channel therebetween; a gate insulating film surrounding side and upper surfaces of the fin-shaped channel; a gate electrode on the gate insulating film; and a two-dimensional semiconductor material layer between the gate insulating film and the gate electrode.

公开(公告)号：US20220262903A1

公开(公告)日：2022-08-18

申请号：US17735475

申请日：2022-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Haeryong KIM ,  Hyeonjin SHIN ,  Seunggeol NAM ,  Seongjun PARK

IPC: H01L29/08 ,  H01L21/285 ,  H01L29/45 ,  H01L29/417 ,  H01L29/04 ,  H01L29/06 ,  H01L29/267 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.