SEMICONDUCTOR DEVICES HAVING GATE ISOLATION LAYERS

    公开(公告)号:US20230290818A1

    公开(公告)日:2023-09-14

    申请号:US18200638

    申请日:2023-05-23

    CPC classification number: H01L29/0649 H01L29/785 H01L29/42364 H01L29/41791

    Abstract: A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer.

    INTEGRATED CIRCUIT DEVICE
    16.
    发明公开

    公开(公告)号:US20240136254A1

    公开(公告)日:2024-04-25

    申请号:US18320423

    申请日:2023-05-18

    Abstract: An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.

    INTEGRATED CIRCUIT DEVICE
    17.
    发明申请

    公开(公告)号:US20230129825A1

    公开(公告)日:2023-04-27

    申请号:US17828327

    申请日:2022-05-31

    Abstract: An integrated circuit (IC) device including a fin-type active region on a substrate and a gate line on the fin-type active and having a first uppermost surface at a first vertical level, an insulating spacer covering a sidewall of the gate line and having a second uppermost surface at the first vertical level, and an insulating guide film covering the second uppermost surface of the insulating spacer may be provided. The gate line may include a multilayered conductive film structure that includes a plurality of conductive patterns and have a top surface defined by the conductive patterns, which includes at least first and second conductive patterns including different materials from each other and a unified conductive pattern that is in contact with a top surface of each of the conductive patterns and has a top surface that defines the first uppermost surface.

    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20210125856A1

    公开(公告)日:2021-04-29

    申请号:US16872955

    申请日:2020-05-12

    Abstract: An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.

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