公开(公告)号：US20240136254A1

公开(公告)日：2024-04-25

申请号：US18320423

申请日：2023-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkoo KANG ,  Wookyung YOU ,  Minjae KANG ,  Koungmin RYU ,  Hoonseok SEO ,  Woojin LEE ,  Junchae LEE

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76898 ,  H01L27/088 ,  H01L29/66439

Abstract: An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.

公开(公告)号：US20250151327A1

公开(公告)日：2025-05-08

申请号：US18666927

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhee KANG ,  Junchae LEE ,  Sungsoo KIM ,  Kyuhee HAN

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate; an active pattern extending on the substrate in a first direction; a plurality of channel layers on the active pattern; a gate structure surrounding the plurality of channel layers, and extending in a second direction that intersects the first direction; blocking insulating layers on both side surfaces of the gate structure, respectively, each of the blocking insulating layers having an upper region having a first thickness and a lower region having a second thickness smaller than the first thickness; source/drain patterns on portions of the active pattern on both sides of the gate structure, the source/drain patterns defining trenches therein; contact structures on the source/drain patterns and filling the trenches; and a metal-semiconductor compound layer between the source/drain patterns and the contact structures.

公开(公告)号：US20240234250A9

公开(公告)日：2024-07-11

申请号：US18320423

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkoo KANG ,  Wookyung YOU ,  Minjae KANG ,  Koungmin RYU ,  Hoonseok SEO ,  Woojin LEE ,  Junchae LEE

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76898 ,  H01L27/088 ,  H01L29/66439

Abstract: An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.