公开(公告)号：US12119288B2

公开(公告)日：2024-10-15

申请号：US17658614

申请日：2022-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbae Kim ,  Sungwoo Park

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/4951 ,  H01L23/49548 ,  H01L24/16 ,  H01L23/3107 ,  H01L23/49513 ,  H01L24/14 ,  H01L2224/1415 ,  H01L2224/16258

Abstract: A semiconductor package includes: a lead frame that includes a first surface and a second surface opposite to the first surface, where the lead frame includes a first lead that extends in a first direction, and a plurality of second leads that are spaced apart from the first lead on both sides of the first lead; at least one semiconductor chip mounted on the first surface of the lead frame by a plurality of bumps; and an encapsulant that encapsulates the lead frame and the at least one semiconductor chip, wherein the first lead has a groove in the first surface that partitions the plurality of bumps in contact with the first lead.

公开(公告)号：US11527470B2

公开(公告)日：2022-12-13

申请号：US16872567

申请日：2020-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shle-Ge Lee ,  Youngbae Kim ,  Ji-Yong Park

IPC: H01L23/49 ,  H01L23/498 ,  H05K1/11 ,  H01L23/31 ,  H01L29/768

Abstract: Disclosed are film packages and methods of fabricating package modules. The film package includes a film substrate that includes a chip region and a peripheral region facing each other in a first direction, a plurality of output pads that are arranged in the first direction on the chip region and on the peripheral region, and a semiconductor chip on the chip region and electrically connected to the output pads. The output pads on the chip region are arranged at regular first intervals along the first direction. The output pads include a plurality of first output pads that are arranged at a first pitch along the first direction on the chip region and a plurality of second output pads on the peripheral region. The second output pads are arranged at a second pitch greater than the first pitch of the first output pads.

公开(公告)号：US11140772B2

公开(公告)日：2021-10-05

申请号：US16689403

申请日：2019-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shle-Ge Lee ,  Youngbae Kim

IPC: H05K1/02 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A printed circuit board can include a base layer, a first surface and a second surface opposite to each other. A first routing layer can be on the first surface and a second routing layer can be on the second surface, the first routing layer can be provided at an upper part of each of the first and second regions and the second routing layer can be provided at a lower part of each of the first and second regions. The upper part of the first region can have a first line-area ratio, the upper part of the second region can have a second line-area ratio, the lower part of the first region can have a third line-area ratio, the lower part of the second region can have a fourth line-area ratio, the second and third line-area ratios can be greater than each of the first and fourth line-area ratios.

公开(公告)号：US10720211B2

公开(公告)日：2020-07-21

申请号：US16458594

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  G11C14/00 ,  H01L27/24 ,  H01L23/528 ,  G11C13/00 ,  G11C5/02 ,  G11C11/00 ,  H01L45/00 ,  H01L27/108

Abstract: A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.

公开(公告)号：US20190027200A1

公开(公告)日：2019-01-24

申请号：US15984914

申请日：2018-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: G11C11/00 ,  H01L27/108 ,  H01L27/24 ,  H01L23/528 ,  H01L49/02 ,  H01L45/00

CPC classification number: G11C11/005 ,  G11C5/025 ,  G11C14/0045 ,  H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10897 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.

公开(公告)号：US11776866B2

公开(公告)日：2023-10-03

申请号：US16994938

申请日：2020-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shle-Ge Lee ,  Youngbae Kim ,  Ae-Nee Jang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/367 ,  H01L23/528 ,  H01L24/14 ,  H01L25/0655 ,  H01L2224/73253

Abstract: A semiconductor module includes a substrate having a central region, an outer region that surrounds the central region, and a middle region disposed between the central and the outer region, a first semiconductor package mounted on the central region of the substrate, a plurality of second semiconductor packages mounted on the middle region of the substrate, and a heat radiation structure disposed on the first semiconductor package and second semiconductor packages. The heat radiation structure includes a first part that is disposed on top surfaces of the first and second semiconductor packages, a second part that surrounds the middle region, a third part that is spaced apart from the second part and surrounds the first semiconductor package, and a fourth part that connects the second part to the third part.

公开(公告)号：US20210183724A1

公开(公告)日：2021-06-17

申请号：US16994938

申请日：2020-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SHLE-GE LEE ,  Youngbae Kim ,  AE-NEE JANG

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/528 ,  H01L23/00

Abstract: A semiconductor module includes a substrate having a central region, an outer region that surrounds the central region, and a middle region disposed between the central and the outer region, a first semiconductor package mounted on the central region of the substrate, a plurality of second semiconductor packages mounted on the middle region of the substrate, and a heat radiation structure disposed on the first semiconductor package and second semiconductor packages. The heat radiation structure includes a first part that is disposed on top surfaces of the first and second semiconductor packages, a second part that surrounds the middle region, a third part that is spaced apart from the second part and surrounds the first semiconductor package, and a fourth part that connects the second part to the third part.

公开(公告)号：US10580469B2

公开(公告)日：2020-03-03

申请号：US16460284

申请日：2019-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  G11C11/00 ,  G11C5/02 ,  G11C14/00 ,  H01L27/108 ,  H01L45/00 ,  H01L27/24 ,  H01L49/02 ,  H01L23/528

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.

公开(公告)号：US20190027482A1

公开(公告)日：2019-01-24

申请号：US15986064

申请日：2018-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGWOO KIM ,  Bong-soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/24

CPC classification number: H01L27/10897 ,  G11C11/005 ,  G11C14/0045 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section on a substrate; a second memory section on the second peripheral circuit section; and a wiring section between the second peripheral circuit section and the second memory section, the first memory section includes a plurality of first memory cells, the first memory cells each including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, the second memory cells each including a variable resistance element and a select element in series, and the wiring section includes a plurality of line patterns, at least one of the line patterns and at least one of the capacitors at the same level from the substrate, the second memory cells are higher from the substrate than the at least one of the capacitors.

公开(公告)号：US09741668B2

公开(公告)日：2017-08-22

申请号：US15357154

申请日：2016-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbae Kim

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/3135 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00014

Abstract: A semiconductor package is provided. The semiconductor includes a lower package and an upper package stacked on the lower package. The lower package includes a package substrate, a semiconductor chip, a mold layer and a residential stress layer. The package substrate has upper and lower surfaces. The semiconductor chip is disposed on the upper surface of the package substrate. The mold layer encapsulates the semiconductor chip. The residual stress layer is disposed on the semiconductor chip. The residual stress layer includes a plastically deformed surface. The residual stress layer has a residual stress to counterbalance warpage of the lower package.