Invention Grant
- Patent Title: Semiconductor packages having residual stress layers and methods of fabricating the same
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Application No.: US15357154Application Date: 2016-11-21
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Publication No.: US09741668B2Publication Date: 2017-08-22
- Inventor: Youngbae Kim
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2014-0084654 20140707
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/10 ; H01L25/00 ; H01L23/31

Abstract:
A semiconductor package is provided. The semiconductor includes a lower package and an upper package stacked on the lower package. The lower package includes a package substrate, a semiconductor chip, a mold layer and a residential stress layer. The package substrate has upper and lower surfaces. The semiconductor chip is disposed on the upper surface of the package substrate. The mold layer encapsulates the semiconductor chip. The residual stress layer is disposed on the semiconductor chip. The residual stress layer includes a plastically deformed surface. The residual stress layer has a residual stress to counterbalance warpage of the lower package.
Public/Granted literature
- US20170069579A1 SEMICONDUCTOR PACKAGES HAVING RESIDUAL STRESS LAYERS AND METHODS OF FABRICATING THE SAME Public/Granted day:2017-03-09
Information query
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