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    Memory device and method of operating the same
    11.
    发明授权
    Memory device and method of operating the same 有权
    存储器件及其操作方法

    公开(公告)号：US09530494B2

    公开(公告)日：2016-12-27

    申请号：US14697244

    申请日：2015-04-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yong-Kyu Lee ,  Dae-Seok Byeon ,  Yeong-Taek Lee ,  Chi-Weon Yoon ,  Hyun-Kook Park ,  Hyo-Jin Kwon

    IPC: G11C16/10 ,  G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0033 ,  G11C13/0035 ,  G11C16/10 ,  G11C2013/0092

    Abstract: A method of operating a memory device, which includes of memory cells respectively arranged in regions where first signal lines and second lines cross each other, includes determining a plurality of pulses so that each of the plurality of pulses that are sequentially applied to a selected memory cell among the plurality of memory cells is changed according to a number of times of executing programming loops. In response to the change of the plurality of pulses, at least one of a first inhibit voltage and a second inhibit voltage is determined so that a voltage level of at least one of the first and second inhibit voltages that are respectively applied to unselected first and second signal lines connected to unselected memory cells among the plurality of memory cells is changed according to the number of times of executing the programming loops.

    Abstract translation: 一种操作存储器件的方法，所述存储器件包括分别布置在第一信号线和第二线彼此交叉的区域中的存储器单元，包括确定多个脉冲，使得多个脉冲中的每一个顺序地施加到选择的存储器 根据执行编程循环的次数来改变多个存储单元之间的单元。 响应于多个脉冲的变化，确定第一禁止电压和第二禁止电压中的至少一个，使得分别施加到未选择的第一和第二禁止电压中的至少一个的电压电平， 连接到多个存储单元之间的未选择的存储单元的第二信号线根据执行编程循环的次数而改变。

    Resistive memory device and method of operating the same
    12.
    发明授权
    Resistive memory device and method of operating the same 有权
    电阻式存储器件及其操作方法

    公开(公告)号：US09183932B1

    公开(公告)日：2015-11-10

    申请号：US14685671

    申请日：2015-04-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyo-Jin Kwon ,  Yeong-Taek Lee ,  Dae-Seok Byeon ,  Yong-Kyu Lee ,  Hyun-Kook Park

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C11/1675 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2213/72

    Abstract: A resistive memory device including multiple resistive memory cells arranged in regions where first signal lines and second signal lines cross each other, and a method of operating the resistive memory device, are provided. The method includes applying a first voltage to a first line, from among unselected first signal lines connected to unselected memory cells, that is not adjacent to a selected first signal line connected to a selected memory cell from among the multiple memory cells; applying a second voltage that is lower than the first voltage to a second line, from among the unselected first signal lines, that is adjacent to the selected first signal line; floating the unselected first signal lines; and applying a third voltage that is higher than the first voltage to the selected first signal line.

    Abstract translation: 一种电阻式存储器件，包括布置在第一信号线和第二信号线彼此交叉的区域中的多个电阻性存储器单元，以及操作该电阻式存储器件的方法。 该方法包括从连接到未选择的存储单元的未选择的第一信号线中的第一行应用第一电压，其不与多个存储器单元中连接到所选择的存储器单元的所选择的第一信号线相邻; 从与所选择的第一信号线相邻的未选择的第一信号线中施加低于第一电压的第二电压到第二线; 浮动未选择的第一条信号线; 以及将高于第一电压的第三电压施加到所选择的第一信号线。

    Resistive memory device and method of operating the same
    15.
    发明授权
    Resistive memory device and method of operating the same 有权
    电阻式存储器件及其操作方法

    公开(公告)号：US09558821B2

    公开(公告)日：2017-01-31

    申请号：US14645701

    申请日：2015-03-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Kook Park ,  Dae-Seok Byeon ,  Yeong-Taek Lee ,  Hyo-Jin Kwon ,  Yong-Kyu Lee

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56 ,  G11C11/16

    CPC classification number: G11C13/0069 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/5607 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2213/71

    Abstract: Provided are a resistive memory device and a method of the resistive memory device. The method of operating the resistive memory device includes performing a pre-read operation on memory cells in response to a write command; performing an erase operation on one or more first memory cells on which a reset write operation is to be performed, determined based on a result of comparing pre-read data from the pre-read operation with write data; and performing set-direction programming on at least some memory cells from among the erased one or more first memory cells and on one or more second memory cells on which a set write operation is to be performed.

    Abstract translation: 提供了电阻式存储器件和电阻式存储器件的方法。 操作电阻式存储器件的方法包括：响应写入命令对存储器单元执行预读取操作; 基于将来自预读取操作的预读数据与写数据进行比较确定的一个或多个要执行复位写操作的第一存储单元执行擦除操作; 并且对被擦除的一个或多个第一存储器单元中的至少一些存储器单元以及要执行设定写入操作的一个或多个第二存储器单元执行设置方向编程。

    Resistive memory device and method programming same
    16.
    发明授权
    Resistive memory device and method programming same 有权
    电阻式存储器件和方法编程相同

    公开(公告)号：US09171617B1

    公开(公告)日：2015-10-27

    申请号：US14667993

    申请日：2015-03-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Kook Park ,  Yeong-Taek Lee ,  Dae-Seok Byeon ,  Yong-Kyu Lee ,  Hyo-Jin Kwon

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0076 ,  G11C2013/0092

    Abstract: A method of programming memory cells of a resistive memory device includes; applying a first current pulse to each of the plurality of memory cells; applying a second current pulse that increases by a first difference compared to the first current pulse to each of the plurality of memory cells to which the first current pulse is applied; and applying a third current pulse that increases by a second difference compared to the second current pulse to each of the plurality of memory cells to which the second current pulse is applied, wherein the first through third current pulses non-linearly increase, and the second difference is greater than the first difference.

    Abstract translation: 一种编程电阻式存储器件的存储单元的方法包括： 对所述多个存储单元中的每一个施加第一电流脉冲; 将与第一电流脉冲相比增加第一差的第二电流脉冲施加到施加了第一电流脉冲的多个存储单元中的每一个; 以及将与所述第二电流脉冲相比增加第二差的第三电流脉冲施加到施加所述第二电流脉冲的所述多个存储单元中的每一个，其中所述第一至第三电流脉冲非线性增加，并且所述第二电流脉冲 差异大于第一个差异。

    Resistive memory device and method of operating the same
    18.
    发明授权
    Resistive memory device and method of operating the same 有权
    电阻式存储器件及其操作方法

    公开(公告)号：US09472282B2

    公开(公告)日：2016-10-18

    申请号：US14979947

    申请日：2015-12-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yong-Kyu Lee ,  Yeong-Taek Lee ,  Dae-Seok Byeon ,  Chi-Weon Yoon

    IPC: G11C13/00 ,  G11C5/06

    CPC classification number: G11C13/0069 ,  G11C5/063 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0064 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

    Abstract: A resistive memory device includes a memory cell array that has a plurality of resistive memory cells that are arranged respectively on regions where a plurality of first signal lines and a plurality of second signal lines cross each other. A write circuit is connected to a selected first signal line that is connected to a selected memory cell from among the plurality of memory cells, and provides pulses to the selected memory cell. A voltage detector detects a node voltage at a connection node between the selected first signal line and the write circuit. A voltage generation circuit generates a first inhibit voltage and a second inhibit voltage that are applied respectively to unselected first and second signal lines connected to unselected memory cells from among the plurality of memory cells, and changes a voltage level of the second inhibit voltage based on the node voltage that is detected.

    Abstract translation: 电阻式存储器件包括存储单元阵列，该存储单元阵列具有分别布置在多个第一信号线和多个第二信号线彼此交叉的区域上的多个电阻存储单元。 写入电路连接到从多个存储器单元中连接到所选择的存储器单元的所选择的第一信号线，并向所选存储单元提供脉冲。 电压检测器检测所选择的第一信号线和写入电路之间的连接节点处的节点电压。 电压产生电路产生分别施加到从多个存储单元中连接到未选择的存储单元的未选择的第一和第二信号线的第一禁止电压和第二禁止电压，并且基于 检测到的节点电压。

    Resistive memory device and method of operating the same to reduce leakage current
    20.
    发明授权
    Resistive memory device and method of operating the same to reduce leakage current 有权
    电阻式存储器件及其操作方法，以减少漏电流

    公开(公告)号：US09361974B2

    公开(公告)日：2016-06-07

    申请号：US14683269

    申请日：2015-04-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yong-Kyu Lee ,  Dae-Seok Byeon ,  Yeong-Taek Lee ,  Chi-Weon Yoon ,  Hyun-Kook Park ,  Hyo-Jin Kwon

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/0023 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0078

    Abstract: A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line.

    Abstract translation: 一种操作存储器件的方法包括从多个第一信号线中确定流过所选择的第一信号线的工作电流的值，所述第一信号线被施加选择电压; 将存储单元阵列划分为n个块，n是大于1的整数，基于工作电流的值; 以及将对应于n个块的具有不同电压电平的抑制电压施加到包括在n个块中的未选择的第二信号线。 每个未选择的第二信号线是由于流过所选择的第一信号线的工作电流和由未选择的第二信号线和所选择的第一信号线寻址的存储器单元而引起的漏电流可能流过的通路。

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