公开(公告)号：US10411062B2

公开(公告)日：2019-09-10

申请号：US15602185

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hyung Kim ,  Seokho Kim ,  SungHyup Kim ,  Jaegeun Kim ,  Taeyeong Kim

IPC: H01L21/67 ,  H01L21/683 ,  H01L23/00 ,  H01L27/146 ,  H01L21/20

Abstract: Disclosed are a substrate bonding apparatus and a method of manufacturing a semiconductor device. The substrate bonding apparatus comprises vacuum pumps, a first chuck engaged with the vacuum pumps and adsorbing a first substrate at vacuum pressure of the vacuum pumps, and a pushing unit penetrating a center of the first chuck and pushing the first substrate away from the first chuck. The first chuck comprises adsorption sectors providing different vacuum pressures in an azimuth direction to the first substrate.

公开(公告)号：US09583373B2

公开(公告)日：2017-02-28

申请号：US13964433

申请日：2013-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Pil-kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Gilheyun Choi

IPC: H01L21/683 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2221/68381 ,  H01L21/78 ,  H01L2224/81

Abstract: A wafer carrier includes a base having a cavity provided at the center of the base and an outer sidewall extending along and away from an edge of the base to define the cavity. The cavity is configured to be filled with an adhesive layer. The wafer carrier is configured to be bonded to a wafer with an adhesive layer in the cavity of base such that the outer sidewall faces and is in contact with an edge of the wafer and the cavity faces a center of the wafer.

Abstract translation: 晶片载体包括具有设置在基部的中心处的空腔的基部和沿着基部的边缘延伸并远离基部的边缘的外侧壁以限定空腔。 空腔构造成填充有粘合剂层。 晶片载体构造成在基底的空腔中与粘合剂层结合到晶片，使得外侧壁面向并与晶片的边缘接触并且空腔面向晶片的中心。

公开(公告)号：US09530706B2

公开(公告)日：2016-12-27

申请号：US14669291

申请日：2015-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil-Kyu Kang ,  Byung Lyul Park ,  Taeyeong Kim ,  Yeun-Sang Park ,  Dosun Lee ,  Ho-Jin Lee ,  Jinho Chun ,  Ju-il Choi ,  Yi Koan Hong

IPC: H01L25/065 ,  H01L21/66 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract translation: 提供具有芯片堆叠和互连端子的半导体器件。 芯片堆叠包括彼此堆叠的第一半导体芯片，第二半导体芯片和第三半导体芯片。 互连端子电耦合到芯片堆叠。 第一半导体芯片包括第一正面和第一背面。 第二半导体芯片包括电耦合到第二电路层并穿透第二半导体芯片的第二前表面，第二背面，第二电路层和贯通电极。 第三半导体芯片包括第三前表面，与第三前表面相对的第三背面和与第三前表面相邻的第三电路层。 第一前表面和第二前表面彼此面对。 第三前表面和第二后侧表面彼此面对。

公开(公告)号：US09070748B2

公开(公告)日：2015-06-30

申请号：US14108771

申请日：2013-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Jumyong Park ,  Jinho Park ,  Kyu-Ha Lee ,  Deok-Young Jung ,  Gilheyun Choi

IPC: H01L21/768

CPC classification number: H01L25/0657 ,  G11C8/00 ,  G11C16/08 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13169 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed.

Abstract translation: 提供半导体器件的导电通孔，其沿垂直方向穿过衬底延伸，导电通孔的第一端延伸穿过衬底的第一表面，使得第一端相对于衬底的第一表面在垂直方向上突出 底物。 绝缘层设置在导电通孔的第一端和基板的第一表面上。 除去掩模层图案的上部，使得在导电通孔的第一端上的绝缘层的封盖部分露出。 去除绝缘层的与导电通孔相隔一定距离的一部分，以在绝缘层中形成凹陷。 同时去除导电通孔第一端上的绝缘层的封盖部分。

公开(公告)号：US12224262B2

公开(公告)日：2025-02-11

申请号：US18638947

申请日：2024-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeyeong Kim ,  Ilyoung Han ,  Hoechul Kim

IPC: H01L23/00

Abstract: A substrate bonding method and apparatus are described. The substrate bonding apparatus is used to bond a first substrate to a second substrate. The bonding apparatus includes a first bonding chuck configured to hold the first substrate on a first surface of the first bonding chuck; a second bonding chuck configured to hold the second substrate on a second surface of the second bonding chuck, the second surface facing the first surface of the first bonding chuck; a seal arranged between the first bonding chuck and the second bonding chuck and adjacent to at least one edge of the first substrate and at least one edge of the second substrate; and a process gas supply device configured to supply a process gas to a bonding space surrounded by the seal.

公开(公告)号：US12175023B2

公开(公告)日：2024-12-24

申请号：US18177122

申请日：2023-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeyeong Kim ,  Jookwan Lee ,  Myunghoon Kwak ,  Yangwook Kim ,  Jihea Park

IPC: G06F3/03 ,  G06F1/16 ,  G06F3/042 ,  G06F3/0482 ,  G06F3/06

Abstract: An electronic device identifies an occurrence of a first event for displaying a first notification message on at least a portion of the display module of the first shape, detects a beginning of shape transformation of the display module from the first shape to the second shape, and maintains the display of the first notification message during the shape transformation of the display module.

公开(公告)号：US11990444B2

公开(公告)日：2024-05-21

申请号：US16933055

申请日：2020-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeyeong Kim ,  Ilyoung Han ,  Hoechul Kim

IPC: H01L23/00

CPC classification number: H01L24/74 ,  H01L24/16 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80091 ,  H01L2224/80095 ,  H01L2224/8012 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80908

Abstract: A substrate bonding method and apparatus are described. The substrate bonding apparatus is used to bond a first substrate to a second substrate. The bonding apparatus includes a first bonding chuck configured to hold the first substrate on a first surface of the first bonding chuck; a second bonding chuck configured to hold the second substrate on a second surface of the second bonding chuck, the second surface facing the first surface of the first bonding chuck; a seal arranged between the first bonding chuck and the second bonding chuck and adjacent to at least one edge of the first substrate and at least one edge of the second substrate; and a process gas supply device configured to supply a process gas to a bonding space surrounded by the seal.

公开(公告)号：US20210143026A1

公开(公告)日：2021-05-13

申请号：US17014335

申请日：2020-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjun Jeon ,  Taeyeong Kim ,  Hoechul Kim ,  Junhong Min

IPC: H01L21/67 ,  H01L23/00 ,  B32B37/00 ,  B32B41/00

Abstract: A substrate bonding apparatus for bonding a first substrate to a second substrate includes a first bonding chuck configured to fix the first substrate to a first surface of the first bonding chuck; a second bonding chuck configured to fix the second substrate to a second surface of the second bonding chuck, the second surface facing the first surface; a process gas injector surrounding at least one selected from the first bonding chuck and the second bonding chuck in a plan view, the process gas injector configured to inject a process gas between the first substrate and the second substrate when respectively disposed on the first bonding chuck and the second bonding chuck; and an air curtain generator disposed at an outside of the process gas injector in the plan view, the air curtain generator configured to inject an air curtain forming gas to form an air curtain surrounding the first substrate and the second substrate.

公开(公告)号：US10950470B2

公开(公告)日：2021-03-16

申请号：US16397552

申请日：2019-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeyeong Kim ,  Minsoo Han ,  Jun Hyung Kim ,  Hoonjoo Na ,  Kwangjin Moon

IPC: H01L21/67 ,  H01L21/687 ,  H01L21/683

Abstract: A substrate bonding apparatus includes a lower chuck that receives a lower substrate and an upper chuck disposed above the lower chuck. An upper substrate is fixed to the upper chuck. The upper chuck and the lower chuck bond the upper substrate to the lower substrate. The upper chuck has an upper convex surface toward the lower chuck. The upper convex surface includes a plurality of first ridges and a plurality of first valleys disposed alternately along an azimuthal direction.

公开(公告)号：US20210057263A1

公开(公告)日：2021-02-25

申请号：US16892492

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoechul Kim ,  Taeyeong Kim ,  Hakjun ` Lee ,  Hoonjoo Na

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/50

Abstract: A substrate bonding apparatus includes a first bonding chuck configured to support a first substrate and a second bonding chuck configured to support a second substrate such that the second substrate faces the first substrate. The first bonding chuck includes a first base, a first deformable plate on the first base and configured to support the first substrate and configured to be deformed such that a distance between the first base and the first deformable plate is varied, and a first piezoelectric sheet on the first deformable plate and configured to be deformed in response to power applied thereto to deform the first deformable plate.