METHOD FOR IMPROVING ANTENNA PERFORMANCE IN ELECTRONIC DEVICE COMPRISING A PLURALITY OF ANTENNAS AND DEVICE THEREOF

    公开(公告)号:US20220342223A1

    公开(公告)日:2022-10-27

    申请号:US17861326

    申请日:2022-07-11

    Abstract: An electronic device according to an embodiment may include at least one display, a main frame to which the at least one display is mounted, a first support frame which is connected to the main frame through a first connector and includes a first antenna, a second support frame which is connected to the main frame through a second connector and includes a second antenna, at least one processor, and at least one sensor. The at least one processor may perform, when the at least one sensor detects that the electronic device is unfolded, wireless communication using the first antenna and the second antenna, and, when the at least one sensor detects that the electronic device is folded, may turn off the first antenna and/or the second antenna, connect first antenna and/or the second antenna to a ground, or shift a resonance frequency of first antenna and/or the second antenna.

    SEMICONDUCTOR DEVICES
    14.
    发明申请

    公开(公告)号:US20220190136A1

    公开(公告)日:2022-06-16

    申请号:US17686504

    申请日:2022-03-04

    Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.

    SEMICONDUCTOR DEVICES
    15.
    发明申请

    公开(公告)号:US20210035975A1

    公开(公告)日:2021-02-04

    申请号:US16849238

    申请日:2020-04-15

    Abstract: A semiconductor device includes a first transistor, a division pattern, and a second transistor sequentially stacked on a substrate. The first transistor includes a first gate structure, a first source/drain layer at each of opposite sides of the first gate structure, and first semiconductor patterns spaced apart from each other in a vertical direction. Each of the first semiconductor patterns extends through the first gate structure and contacts the first source/drain layer. The division pattern includes an insulating material. The second transistor includes a second gate structure, a second source/drain layer at each of opposite sides of the second gate structure, and second semiconductor patterns spaced apart from each other in the vertical direction. Each of the second semiconductor patterns extends through the second gate structure and contacts the second source/drain layer. The first source/drain layer does not directly contact the second source/drain layer.

    METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE
    16.
    发明申请
    METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号:US20160049335A1

    公开(公告)日:2016-02-18

    申请号:US14822077

    申请日:2015-08-10

    Inventor: Bin LIU Sungmin KIM

    Abstract: Methods for manufacturing a semiconductor device including a field effect transistor include forming first fins protruding from a substrate including a first region and a second region, the first fins including silicon-germanium (SiGe), forming a first mask pattern to expose the first fins disposed in the second region, the first mask pattern covering the first fins disposed in the first region, oxidizing the first fins in the second region to form second fins in the second region, and forming germanium (Ge)-rich layers each disposed on a surface of a respective one of the second fins.

    Abstract translation: 制造包括场效应晶体管的半导体器件的方法包括形成从包括第一区域和第二区域的衬底突出的第一鳍片,所述第一鳍片包括硅 - 锗(SiGe),形成第一掩模图案以暴露设置的第一鳍片 在第二区域中,覆盖设置在第一区域中的第一鳍片的第一掩模图案,在第二区域中氧化第一鳍片以在第二区域中形成第二鳍片,并且形成各自设置在表面上的锗(Ge) 的第二鳍片中的相应一个。

    ELECTRONIC DEVICE COMPRISING CAMERA MODULE

    公开(公告)号:US20240380975A1

    公开(公告)日:2024-11-14

    申请号:US18779817

    申请日:2024-07-22

    Abstract: An electronic device according to an embodiment may include a first camera module including a first driving circuit, a sub processor, and a main processor functionally connected to the first camera module and the sub processor, wherein the main processor is configured to generate a first clock signal and transmit the same to the first camera module while a first camera included in the first camera module is in an activated state, transmit a first control signal to the sub processor in response to occurrence of a predetermined event in a sleep state, and the sub processor is configured to generate a second clock signal and transmit the same to the first camera module while the main processor is in a sleep state in response to receipt of the first control signal. In addition to this, various embodiments identified thorough the specification are possible.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

    公开(公告)号:US20230261079A1

    公开(公告)日:2023-08-17

    申请号:US17987126

    申请日:2022-11-15

    CPC classification number: H01L29/42392 H01L29/78696 H01L29/0847 H01L29/6656

    Abstract: Disclosed are semiconductor devices and fabrication methods thereof. The semiconductor device includes a substrate including first and second regions, a device isolation pattern in the substrate, a lower separation dielectric pattern on the first region of the substrate, first channel patterns on the lower separation dielectric pattern, a first gate electrode on the first channel patterns and including a first gate part between the lower separation dielectric pattern and a lowermost first channel pattern, and first source/drain patterns on opposite sides of the first gate electrode and in contact with lateral surfaces of the first channel patterns. A bottom surface of the lower separation dielectric pattern is at a level higher than or equal to that of a bottom surface of the device isolation pattern. A top end of the lower separation dielectric pattern is at a level higher than that of a bottom surface of the first gate part.

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