公开(公告)号：US20220246089A1

公开(公告)日：2022-08-04

申请号：US17712687

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghyun SONG ,  Sangtae HAN ,  Huigyeong AHN ,  Changsun KANG ,  Mijin KIM ,  Seongjun KIM ,  Changjun PARK ,  Seunghee OH ,  Kyoree LEE ,  Mihyun LEE

IPC: G09G3/32

Abstract: A display apparatus is provided. The display apparatus includes a substrate having a data line disposed thereon, a plurality of pixel modules arranged in a matrix format on the substrate, and a driver providing a digital data signal through the data line to each of the pixel modules. Each of the pixel modules may include a light emitting layer in which a plurality of light emitting diode (LED) devices form a pixel, a driving layer comprising a display driver integrated circuit (DDI) below the light emitting layer and generating a driving signal to drive the LED devices, and a substrate layer, between the driving layer and the substrate, comprising a data input pad to receive the data signal and transmit the data signal to the DDI and a data output pad to provide the data signal to another adjacent pixel module.

公开(公告)号：US20250031360A1

公开(公告)日：2025-01-23

申请号：US18905663

申请日：2024-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Seunghyun SONG ,  Saehan PARK ,  Seungyoung LEE ,  Inchan HWANG

IPC: H10B10/00 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

公开(公告)号：US20240088219A1

公开(公告)日：2024-03-14

申请号：US18452858

申请日：2023-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pilkwang KIM ,  Seunghyun SONG ,  Yoonsuk KIM ,  Gwangjun KIM ,  Jaemin KIM

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active region, a plurality of channel layers spaced apart from each other on the active region, a gate structure including a gate dielectric layer and a gate electrode, and source/drain regions on both sides of the gate structure. The gate structure includes an upper portion and lower portions. A first lower portion of the lower portions has a first lower surface, a first upper surface, and first and second side surfaces. Each of the first and second side surfaces includes a first inclined portion sloped at a first acute angle from the first lower surface and a second inclined portion sloped at a second acute angle from the first upper surface. The gate dielectric layer includes portions disposed between the gate electrode and the plurality of channel layers and between the gate electrode and the source/drain regions.

公开(公告)号：US20230037833A1

公开(公告)日：2023-02-09

申请号：US17970777

申请日：2022-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Seunghyun SONG ,  Kang III SEO ,  Hwichan JUN ,  lnchan HWANG

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

公开(公告)号：US20220109014A1

公开(公告)日：2022-04-07

申请号：US17350543

申请日：2021-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghyun SONG ,  JUNETAEG LEE

IPC: H01L27/146

Abstract: Disclosed is an image sensor including a first substrate having first and second surfaces opposite to each other and including a pixel array area that includes unit pixel regions, a pad area that surrounds the pixel array area, and an optical black area between the pixel array area and the pad area, a dielectric pattern on the first surface of the first substrate, and a light-shield pattern on a top surface of the dielectric pattern on the optical black area. The first substrate includes first and second trenches recessed from the first surface. The dielectric pattern includes a first part filling the first trench and defining the unit pixel regions, a second part filling the second trench, and a third part on the first surface of the first substrate and connected to the first and second parts.

公开(公告)号：US20230261079A1

公开(公告)日：2023-08-17

申请号：US17987126

申请日：2022-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghyun SONG ,  Pilkwang KIM ,  Joohyung YOU ,  Sungmin KIM ,  Yonghee PARK ,  Young-Seok SONG ,  Takeshi OKAGAKI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0847 ,  H01L29/6656

Abstract: Disclosed are semiconductor devices and fabrication methods thereof. The semiconductor device includes a substrate including first and second regions, a device isolation pattern in the substrate, a lower separation dielectric pattern on the first region of the substrate, first channel patterns on the lower separation dielectric pattern, a first gate electrode on the first channel patterns and including a first gate part between the lower separation dielectric pattern and a lowermost first channel pattern, and first source/drain patterns on opposite sides of the first gate electrode and in contact with lateral surfaces of the first channel patterns. A bottom surface of the lower separation dielectric pattern is at a level higher than or equal to that of a bottom surface of the device isolation pattern. A top end of the lower separation dielectric pattern is at a level higher than that of a bottom surface of the first gate part.

公开(公告)号：US20220109046A1

公开(公告)日：2022-04-07

申请号：US17146136

申请日：2021-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Seunghyun SONG ,  Kang III SEO ,  Hwichan JUN ,  Inchan HWANG

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

公开(公告)号：US20250056873A1

公开(公告)日：2025-02-13

申请号：US18930077

申请日：2024-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghyun SONG ,  Seungyoung Lee ,  Saehan Park

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/423 ,  H10B10/00

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a cross-coupled gate circuit in a three-dimensional (3D) stack including a plurality of transistors, a first gate line of a first transistor among the plurality of transistors connected to a fourth gate line of a fourth transistor among the plurality of transistors, a second gate line of a second transistor among the plurality of transistors connected to a third gate line of a third transistor among the plurality of transistors, a first conductor connecting the first gate line and the fourth gate line, a second conductor connecting the second gate line and the third gate line. The first gate line and the second gate line are arranged above the third gate line and the fourth gate line, respectively.

公开(公告)号：US20240363634A1

公开(公告)日：2024-10-31

申请号：US18732767

申请日：2024-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inchan HWANG ,  Seunghyun SONG ,  Byounghak HONG

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: A multi-stack semiconductor device includes: a lower-stack transistor structure including a lower active region and a lower gate structure, the lower active region including a lower channel structure, and the lower gate structure surrounding the lower channel structure; an upper-stack transistor structure vertically stacked above the lower-stack transistor structure, and including an upper active region and an upper gate structure, the upper active region including an upper channel structure, and the upper gate structure surrounding the upper channel structure; and at least one gate contact plug contacting a top surface of the lower gate structure, wherein the lower gate structure and the upper gate structure have a substantially same size in a plan view, and wherein the lower gate structure is not entirely overlapped by the upper gate structure in a vertical direction.

公开(公告)号：US20240096960A1

公开(公告)日：2024-03-21

申请号：US18239248

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghyun SONG ,  Minsuk Kim ,  Pilkwang Kim ,  Takeshi Okagaki ,  Geunmyeong Kim ,  Ahyoung kim ,  Yoonsuk Kim

IPC: H01L29/08 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a back side interconnection structure extending in a first horizontal direction. An active substrate includes a fin-type active area extending in the first horizontal direction on the back side interconnection structure. A metal silicide film is between the back side interconnection structure and the active substrate. A plurality of gate structures extends in a second horizontal direction perpendicular to the first horizontal direction on the active substrate. A first source/drain area and a second source/drain area are spaced apart from each other in the first horizontal direction with the plurality of gate structures therebetween on the active substrate. The first source/drain area directly contacts the active substrate. The second source/drain area is spaced apart from the active substrate and insulated from the active substrate.