公开(公告)号：US10950499B2

公开(公告)日：2021-03-16

申请号：US16868811

申请日：2020-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-yeong Joe ,  Seok-hoon Kim ,  Jeong-ho Yoo ,  Seung-hun Lee ,  Geun-hee Jeong

IPC: H01L21/768 ,  H01L23/528

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.

公开(公告)号：US09755076B2

公开(公告)日：2017-09-05

申请号：US15378178

申请日：2016-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-hoon Kim ,  Jin-bum Kim ,  Kwan-heum Lee ,  Byeong-chan Lee ,  Cho-eun Lee ,  Su-jin Jung

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.