公开(公告)号：US11003393B2

公开(公告)日：2021-05-11

申请号：US16807405

申请日：2020-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyeon Shin ,  Sangwan Nam ,  Sangwon Park

IPC: G11C7/00 ,  G06F3/06

Abstract: A method includes performing a first sensing operation to sense write setting data stored in first memory cells of a first memory plane and store first read setting data in a first page buffer circuit of the first memory plane, performing a second sensing operation to sense the write setting data stored in second memory cells of a second memory plane and store second read setting data in a second page buffer circuit of the second memory plane and performing a dump-down operation to store restored setting data corresponding to the write setting data in a buffer based on the first read setting data and the second read setting data.

公开(公告)号：US20210096967A1

公开(公告)日：2021-04-01

申请号：US16865948

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G06F11/20 ,  G11C16/04 ,  G11C16/08

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US20210035650A1

公开(公告)日：2021-02-04

申请号：US17012135

申请日：2020-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyeon SHIN ,  Sangwan Nam ,  Sangwon Park

IPC: G11C16/34 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  G11C16/10 ,  G11C16/26

Abstract: Method of controlling initialization of nonvolatile memory device, where nonvolatile memory device includes memory cell region including first metal pad and peripheral circuit region including second metal pad and vertically connected to memory cell region by first and second metal pads, includes performing first sensing operation to sense write setting data stored in first memory cells in memory cell region of first memory plane and store first read setting data in first page buffer circuit in peripheral circuit region of first memory plane, performing second sensing operation to sense write setting data stored in second memory cells in memory cell region of second memory plane and store second read setting data in second page buffer circuit in peripheral circuit region of second memory plane and performing dump-down operation to store restored setting data in buffer based on first read setting data and second read setting data.

公开(公告)号：US10530550B2

公开(公告)日：2020-01-07

申请号：US14781823

申请日：2014-04-01

Applicant: Samsung Electronics Co., Ltd. ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Hyojin Lee ,  Chungyong Lee ,  Hoondong Noh ,  Younsun Kim ,  Juho Lee ,  Hyoungju Ji ,  Sangwon Park ,  Ilkyu Choi

IPC: H04L5/00 ,  H04B7/06 ,  H04L1/00 ,  H04W72/04 ,  H04B7/0456

Abstract: Provided is a method and apparatus for transmitting and receiving channel-related information. A method for allowing a terminal to transmit channel-related information according to an embodiment of the present invention may include: receiving a first signal including data and a reference signal; estimating a modulation order corresponding to a channel state from the first signal; and transmitting channel-related information including a first modulation order indicator (MOI), which indicates the estimated modulation order, to a base station. Accordingly, signals can be efficiently transmitted and received.

公开(公告)号：US12131784B2

公开(公告)日：2024-10-29

申请号：US17742874

申请日：2022-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon Park ,  Bongsoon Lim ,  Byungsoo Kim

IPC: G11C16/00 ,  G11C5/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/16 ,  G11C5/063 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30

Abstract: A non-volatile memory device includes a plurality of word lines stacked above a substrate in a vertical direction; erase control lines that are spaced apart from each other in a first direction and extend in a second direction; a pass transistor circuit including a first pass transistor connected to a first group of erase control lines and a second pass transistor connected to a second group of erase control lines; and a memory cell array including a plurality of blocks. The first group of erase control lines are relatively close to a word line cut region and the second group of erase control lines are relatively far from the word line cut region. Each of the plurality of blocks includes a plurality of channel structures connected to the word lines and the erase control lines and each channel structure extends in the vertical direction.

公开(公告)号：US12100452B2

公开(公告)日：2024-09-24

申请号：US17742879

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuihan Ko ,  Sangwon Park ,  Minyong Kim ,  Jekyung Choi ,  Junho Choi

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26

Abstract: A non-volatile memory device is provided. The memory device includes: word lines stacked on a substrate; a string select lines on the word lines, the string select lines being spaced apart from each other in a first horizontal direction and extending in a second horizontal direction; and a memory cell array including memory blocks, each of which includes memory cells connected to the word lines and the string select lines. The string select lines include a first string select line, and a second string select line which is farther from a word line cut region than the first string select line, and a program operation performed on second memory cells connected to a selected word line and the second string select line is performed before a program operation performed on first memory cells connected to the selected word line and the first string select line.

公开(公告)号：US11929118B2

公开(公告)日：2024-03-12

申请号：US17748156

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Yohan Lee ,  Sangwon Park ,  Jaeduk Yu

IPC: G11C16/04 ,  G11C7/10 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/0433 ,  G11C7/1039 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26

Abstract: Provided is a non-volatile memory device including a memory cell array including cell strings each including memory cells and a string select transistor connected to a string select line; a page buffer circuit including page buffers each including a forcing latch configured to store forcing information; and a control logic circuit configured to, during a program operation on a selected word line, control at least two of a first voltage applied to the string select line in a first interval before a bit line forcing operation for transferring the forcing information to the selected cell string, a second voltage applied to the string select line in a second interval in which the bit line forcing operation is performed, and a third voltage applied to the string select line in a third interval after the bit line forcing operation is performed, to be different from each other.

公开(公告)号：US11797405B2

公开(公告)日：2023-10-24

申请号：US17935502

申请日：2022-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G11C16/10 ,  G06F11/20 ,  G11C16/04 ,  G11C16/08 ,  H10B41/27 ,  H10B43/27

CPC classification number: G06F11/2094 ,  G11C16/0483 ,  G11C16/08 ,  G06F2201/85 ,  H10B41/27 ,  H10B43/27

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US11626165B2

公开(公告)日：2023-04-11

申请号：US17888743

申请日：2022-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yohan Lee ,  Sangwan Nam ,  Sangwon Park

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08 ,  G11C16/30

Abstract: A memory device includes a cell area including memory blocks, and a peripheral circuit area including peripheral circuits that execute an erase operation for each of the memory blocks. Each memory block includes word lines that are stacked on a substrate, channel structures penetrate through the word lines, and a source region that is disposed on the substrate and connected to the channel structures. During the erase operation in which an erase voltage is provided to the source region of a target memory block among the memory blocks, the peripheral circuits reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time, and to reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first time.

公开(公告)号：US20220093179A1

公开(公告)日：2022-03-24

申请号：US17234955

申请日：2021-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yohan Lee ,  Sangwan Nam ,  Sangwon Park

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/08 ,  G11C16/04

Abstract: A memory device includes memory blocks, each including memory cells, and peripheral circuits that control the memory blocks and execute an erase operation for each of the memory blocks. Each memory block includes word lines stacked on a substrate, channel structures extending perpendicular to an upper surface of the substrate and penetrating through the word lines, and a source region disposed on the substrate and connected to the channel structures. During an erase operation in which an erase voltage is input to the source region of a target memory block, the peripheral circuits reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time and reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first in time.