公开(公告)号：US10283360B2

公开(公告)日：2019-05-07

申请号：US15886372

申请日：2018-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Sic Yoon ,  Ki Seok Lee ,  Dong Oh Kim ,  Yong Jae Kim

IPC: H01L21/027 ,  G03F1/38 ,  H01L21/02 ,  H01L27/02 ,  H01L27/108

Abstract: Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, forming a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.

公开(公告)号：US10026614B2

公开(公告)日：2018-07-17

申请号：US15291415

申请日：2016-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan Sic Yoon ,  Ki Seok Lee ,  Dong Oh Kim

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/8234

Abstract: A method for manufacturing a semiconductor device includes forming features of a first mold pattern on a substrate including a first region and a second region, and forming a first insulation layer covering the first mold pattern from the first region to the second region. The method further includes forming a photoresist pattern on the first insulation layer in the second region, forming a second insulation layer covering the first insulation layer in the first region and the photoresist pattern in the second region from the first region to the second region, etching the second insulation layer, removing the photoresist pattern, and forming a first double patterning technology pattern having a first width in the first region and a second DPT pattern having a second width in the second region, wherein the second width is different from the first width.

公开(公告)号：US20240365532A1

公开(公告)日：2024-10-31

申请号：US18507204

申请日：2023-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Jin Park ,  Jun Soo Kim ,  Ji Ho Park ,  Ki Seok Lee ,  Myeong-Dong Lee ,  Ho Sang Lee

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

Abstract: Semiconductor memory devices including capacitors and methods for manufacturing thereof. The semiconductor memory device may include a substrate, an element isolation pattern defining an active area in the substrate, a first conductive pattern on the substrate and the element isolation pattern, and extending in a first direction, wherein the first conductive pattern is connected to a first portion of the active area, a capacitor structure on the substrate and the element isolation pattern and connected to a second portion of the active area, a gate trench defined in the substrate and the element isolation pattern and extending in a second direction, wherein a first trench width of a portion of the gate trench in the active area is greater than a second trench width of a portion of the gate trench in the element isolation pattern.

公开(公告)号：US20240357796A1

公开(公告)日：2024-10-24

申请号：US18543261

申请日：2023-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Jin Lim ,  Jin Woo Han ,  Ki Seok Lee

IPC: H10B12/00 ,  H10B53/30

CPC classification number: H10B12/377 ,  H01L28/55 ,  H10B12/36 ,  H10B12/50 ,  H10B53/30

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes a substrate, a channel region on the substrate, first and second source/drain regions electrically connected to the channel region, a gate electrode that extends in a first direction and is on the channel region, a conductive line that extends in a second direction intersecting the first direction and is electrically connected to the second source/drain region, and a capacitor structure electrically connected to the first source/drain region on the substrate. The capacitor structure may include a plurality of first electrodes stacked and spaced apart from each other in a third direction perpendicular to an upper surface of the substrate, a plurality of trenches extending into the plurality of first electrodes, a capacitor dielectric film that extends along side walls of each of the plurality of trenches, and a plurality of second electrodes in the plurality of trenches, respectively.

公开(公告)号：US12080791B2

公开(公告)日：2024-09-03

申请号：US17400218

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Tae Ryu ,  Sang Hoon Uhm ,  Ki Seok Lee ,  Min Su Lee ,  Won Sok Lee ,  Min Hee Cho

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/24 ,  H10B12/00

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/24 ,  H10B12/30

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

公开(公告)号：US20230180455A1

公开(公告)日：2023-06-08

申请号：US17933875

申请日：2022-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Geun Choi ,  Ki Seok Lee

IPC: H01L27/108

CPC classification number: H01L27/10805

Abstract: According to some embodiments of the present inventive concept, a semiconductor memory device includes a plurality of mold insulating layers on a substrate and spaced apart from one another, a plurality of semiconductor patterns which are between respective ones of the plurality of mold insulating layers adjacent to each other, a plurality of gate electrodes, on respective ones of the plurality of semiconductor patterns, an information storage element which includes a first electrode electrically connected to each of the plurality of semiconductor patterns, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode, a bit line on the substrate and contacts the semiconductor pattern, and an insulating buffer film between the first electrodes and the second electrode and on a sidewall of a respective one of the plurality of mold insulating layers.

公开(公告)号：US11121134B2

公开(公告)日：2021-09-14

申请号：US16860276

申请日：2020-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ho Lee ,  Eun A Kim ,  Ki Seok Lee ,  Jay-Bok Choi ,  Keun Nam Kim ,  Yong Seok Ahn ,  Jin-Hwan Chun ,  Sang Yeon Han ,  Sung Hee Han ,  Seung Uk Han ,  Yoo Sang Hwang

IPC: H01L21/00 ,  H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

公开(公告)号：US10998324B2

公开(公告)日：2021-05-04

申请号：US16890456

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook Jung ,  Dong Oh Kim ,  Seok Han Park ,  Chan Sic Yoon ,  Ki Seok Lee ,  Ho In Lee ,  Ju Yeon Jang ,  Je Min Park ,  Jin Woo Hong

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/108 ,  H01L29/10 ,  H01L21/8238 ,  H01L23/535

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US10332894B2

公开(公告)日：2019-06-25

申请号：US15828934

申请日：2017-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook Jung ,  Dong Oh Kim ,  Seok Han Park ,  Chan Sic Yoon ,  Ki Seok Lee ,  Ho In Lee ,  Ju Yeon Jang ,  Je Min Park ,  Jin Woo Hong

IPC: H01L27/11 ,  H01L29/10 ,  H01L27/108 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US10199328B2

公开(公告)日：2019-02-05

申请号：US15258138

申请日：2016-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan Sic Yoon ,  Ki Seok Lee

IPC: H01L23/535 ,  H01L23/485 ,  H01L29/06 ,  H01L29/423 ,  H01L27/108

Abstract: A semiconductor device includes a first contact plug on a substrate, a first lower electrode disposed on the first contact plug and extended in a thickness direction of the substrate, a first supporter pattern on the first lower electrode and including an upper surface and a lower surface, the upper surface of the first supporter pattern being higher than a top surface of the first lower electrode, a dielectric film on the first lower electrode, the upper surface of the first supporter pattern and the lower surface of the first supporter pattern and an upper electrode disposed on the dielectric film.