知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

31 records (took 0.016 seconds)

    SEMICONDUCTOR MEMORY DEVICE
    11.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240147701A1

    公开(公告)日：2024-05-02

    申请号：US18238790

    申请日：2023-08-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Eunju CHO ,  Keunnam KIM ,  Seokhan PARK ,  Seok-Ho SHIN ,  Joongchan SHIN ,  Heechan YOON

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

    Abstract: A semiconductor memory device may include a substrate including a cell array region and a connection region, bit lines provided on the substrate and extending in a first direction, first and second active patterns alternately arranged in the first direction on each of the bit lines, back-gate electrodes disposed between adjacent ones of the first and second active patterns and extended in a second direction to cross the bit lines, first and second word lines disposed adjacent to the first and second active patterns respectively and extending in the second direction, and a shielding conductive pattern including line portions, which are respectively disposed between adjacent ones of the bit lines, and a plate portion, which is connected in common to the line portions. A length of the line portions of the shielding conductive pattern in the first direction may be shorter than that of the bit lines.

    SEMICONDUCTOR MEMORY DEVICE
    12.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230363143A1

    公开(公告)日：2023-11-09

    申请号：US18182539

    申请日：2023-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok LEE ,  Moonyoung JEONG ,  Keunnam KIM ,  Seokhan PARK

    IPC: H10B12/00 ,  H10B80/00

    CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/05 ,  H10B80/00

    Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, first and second active patterns disposed on the bit line, a back-gate electrode, which is disposed between the first and second active patterns and is extended in a second direction to cross the bit line, a first word line, which is provided at a side of the first active pattern and is extended in the second direction, a second word line, which is provided at an opposite side of the second active pattern and is extended in the second direction, and contact patterns coupled to the first and second active patterns, respectively.

    SEMICONDUCTOR MEMORY DEVICE
    13.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210043629A1

    公开(公告)日：2021-02-11

    申请号：US16880230

    申请日：2020-05-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung KIM ,  Taehyun AN ,  Kiseok LEE ,  Keunnam KIM ,  Yoosang HWANG

    IPC: H01L27/108 ,  G11C5/06

    Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

    SEMICONDUCTOR DEVICES
    15.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190363088A1

    公开(公告)日：2019-11-28

    申请号：US16532857

    申请日：2019-08-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ho-In RYU ,  Taiheui CHO ,  Keunnam KIM ,  Kyehee YEOM ,  Junghwan PARK ,  Hyeon-Woo JANG

    IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423

    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

    SEMICONDUCTOR DEVICE
    16.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240431122A1

    公开(公告)日：2024-12-26

    申请号：US18623732

    申请日：2024-04-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hongjun LEE ,  Kiseok LEE ,  Hyungeun CHOI ,  Keunnam KIM ,  Incheol NAM

    IPC: H10B80/00 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor device includes a lower chip structure, and an upper chip structure on the lower chip structure. The lower chip structure includes a memory structure, a lower interconnection structure electrically connected to the memory structure, and a lower bonding pad electrically connected to the lower interconnection structure. The upper chip structure includes an upper base, a peripheral transistor on the upper base, a first upper interconnection structure electrically connected to the peripheral transistor, on the upper base, a through-via penetrating through the upper base and electrically connected to the first upper interconnection structure, an upper bonding pad bonded to the lower bonding pad, below the upper base, and an intermediate connection structure electrically connecting the upper bonding pad and the through-via, between the upper base and the lower chip.

    SEMICONDUCTOR DEVICE
    17.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240266408A1

    公开(公告)日：2024-08-08

    申请号：US18507224

    申请日：2023-11-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM

    IPC: H01L29/417 ,  H01L27/088

    CPC classification number: H01L29/41741 ,  H01L27/088

    Abstract: A semiconductor device includes a device isolation part on a substrate and defining active regions that are two-dimensionally disposed in first and second directions, the active regions each extending in the first direction; first and second word lines crossing the active regions in the second direction and adjacent to each other in the first direction; a first impurity region in the active region between the first and second word lines; a second impurity region in the active region at one side of the first word line and spaced apart from the first impurity region; a first conductive pad in contact with the first impurity region; a second conductive pad in contact with the second impurity region; a bit line on the first conductive pad and extending in the first direction; a storage node contact structure on the second conductive pad; and a landing pad on the storage node contact structure.

    SEMICONDUCTOR MEMORY DEVICE
    18.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240147707A1

    公开(公告)日：2024-05-02

    申请号：US18242817

    申请日：2023-09-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taegyu KANG ,  Taehyuk KIM ,  Seok-Ho SHIN ,  Keunnam KIM ,  Seokhan PARK ,  Joongchan SHIN ,  Kiseok LEE

    IPC: H10B12/00 ,  H01L23/522

    CPC classification number: H10B12/50 ,  H01L23/5225 ,  H10B12/09 ,  H10B12/315 ,  H10B12/482

    Abstract: A semiconductor memory device may include a substrate including a cell array region and a peripheral circuit region, an active pattern on the cell array region of the substrate, a peripheral active pattern on the peripheral circuit region of the substrate, a peripheral gate electrode disposed on a top surface of the peripheral active pattern, a first interlayer insulating pattern provided on the cell array region to cover a top surface of the active pattern, a first etch stop layer covering the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness, and a second interlayer insulating pattern disposed on the first etch stop layer and in the peripheral circuit region. In the cell array region, the second interlayer insulating pattern may have a top surface, which is located at substantially the same level as a top surface of the first etch stop layer.

    INTEGRATED CIRCUIT DEVICE
    20.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20230262962A1

    公开(公告)日：2023-08-17

    申请号：US18107589

    申请日：2023-02-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Miso MYUNG ,  Keunnam KIM ,  Euna KIM ,  Huijung KIM ,  Sangho LEE

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/02

    Abstract: An integrated circuit device includes a substrate having an active area, bit line structures on the substrate, the bit line structures including an insulating spacer on each sidewall thereof, a buried contact between the bit line structures, the buried contact being connected to the active area, an insulation capping pattern on each of the bit line structures, a barrier conductive layer covering side surfaces of the insulation capping pattern, and an upper surface and side surfaces of the insulating spacer, and a landing pad electrically connected to the buried contact, the landing pad vertically overlapping one of the bit line structures on the insulation capping pattern and the barrier conductive layer.

Patent Agency Ranking