公开(公告)号：US20240147701A1

公开(公告)日：2024-05-02

申请号：US18238790

申请日：2023-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Eunju CHO ,  Keunnam KIM ,  Seokhan PARK ,  Seok-Ho SHIN ,  Joongchan SHIN ,  Heechan YOON

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor memory device may include a substrate including a cell array region and a connection region, bit lines provided on the substrate and extending in a first direction, first and second active patterns alternately arranged in the first direction on each of the bit lines, back-gate electrodes disposed between adjacent ones of the first and second active patterns and extended in a second direction to cross the bit lines, first and second word lines disposed adjacent to the first and second active patterns respectively and extending in the second direction, and a shielding conductive pattern including line portions, which are respectively disposed between adjacent ones of the bit lines, and a plate portion, which is connected in common to the line portions. A length of the line portions of the shielding conductive pattern in the first direction may be shorter than that of the bit lines.