公开(公告)号：US20240147707A1

公开(公告)日：2024-05-02

申请号：US18242817

申请日：2023-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taegyu KANG ,  Taehyuk KIM ,  Seok-Ho SHIN ,  Keunnam KIM ,  Seokhan PARK ,  Joongchan SHIN ,  Kiseok LEE

IPC: H10B12/00 ,  H01L23/522

CPC classification number: H10B12/50 ,  H01L23/5225 ,  H10B12/09 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor memory device may include a substrate including a cell array region and a peripheral circuit region, an active pattern on the cell array region of the substrate, a peripheral active pattern on the peripheral circuit region of the substrate, a peripheral gate electrode disposed on a top surface of the peripheral active pattern, a first interlayer insulating pattern provided on the cell array region to cover a top surface of the active pattern, a first etch stop layer covering the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness, and a second interlayer insulating pattern disposed on the first etch stop layer and in the peripheral circuit region. In the cell array region, the second interlayer insulating pattern may have a top surface, which is located at substantially the same level as a top surface of the first etch stop layer.