公开(公告)号：US20190309415A1

公开(公告)日：2019-10-10

申请号：US16200149

申请日：2018-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonock Han ,  Wonwoong Chung ,  Keum Seok Park ,  Pankwi Park ,  Jeongho Yoo ,  Younjoung Cho ,  Byung Koo Kong ,  Mijeong Kim ,  Jin Wook Lee ,  Changeun Jang

IPC: C23C16/448 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor device includes disposing a gas-storage cylinder storing monochlorosilane within a gas supply unit. The monochlorosilane is supplied from the gas-storage cylinder into a process chamber to form a silicon containing layer therein. The gas-storage cylinder includes manganese.

公开(公告)号：US09553190B2

公开(公告)日：2017-01-24

申请号：US14673519

申请日：2015-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keum Seok Park ,  Jungho Yoo ,  Jinyeong Joe ,  Bonyoung Koo ,  Dongsuk Shin ,  Hongsik Yoon ,  Byeongchan Lee

IPC: H01L29/772 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

Abstract translation: 半导体器件包括从衬底突出的有源图案，在有源图案上交叉的栅极结构以及设置在栅极结构的相对侧上的有源图案上的源极/漏极区域。 源极/漏极区域中的每一个包括接触有源图案的第一外延图案和第一外延图案上的第二外延图案。 第一外延图案包括具有与衬底相同的晶格常数的材料，并且第二外延图案包括具有大于第一外延图案的晶格常数的晶格常数的材料。

公开(公告)号：US11004976B2

公开(公告)日：2021-05-11

申请号：US16351328

申请日：2019-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L21/335

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US10883173B2

公开(公告)日：2021-01-05

申请号：US16200149

申请日：2018-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonock Han ,  Wonwoong Chung ,  Keum Seok Park ,  Pankwi Park ,  Jeongho Yoo ,  Younjoung Cho ,  Byung Koo Kong ,  Mijeong Kim ,  Jin Wook Lee ,  Changeun Jang

IPC: F17C1/00 ,  F17C13/02 ,  C23C16/448 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor device includes disposing a gas-storage cylinder storing monochlorosilane within a gas supply unit. The monochlorosilane is supplied from the gas-storage cylinder into a process chamber to form a silicon containing layer therein. The gas-storage cylinder includes manganese.

公开(公告)号：US10263109B2

公开(公告)日：2019-04-16

申请号：US14995215

申请日：2016-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L21/8234 ,  H01L21/44 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US20180355510A1

公开(公告)日：2018-12-13

申请号：US15869905

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum Seok Park ,  Gyeom Kim ,  Yi Hwan Kim ,  Sun Jung Kim ,  Pan Kwi Park ,  Jeong Ho Yoo

IPC: C30B25/12 ,  C23C16/458

CPC classification number: C30B25/12 ,  C23C16/4585 ,  H01L29/0847 ,  H01L29/66795

Abstract: A semiconductor process chamber includes a susceptor, a base plate surrounding the susceptor, a liner on an inner sidewall of the base plate, and a preheat ring between the susceptor and the base plate and coplanar with the susceptor. The process chamber further includes an upper dome coupled to the base plate and covering an upper surface of the susceptor. The upper dome includes a first section on an upper surface of the base plate and a second section extending from the first section and overlapping the susceptor. The first section includes a first region on the upper surface of the base plate, a second region extending from the first region past the base plate, and a third region extending from the second region with a decreasing thickness to contact the second section.