公开(公告)号：US12029024B2

公开(公告)日：2024-07-02

申请号：US17538064

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source/drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source/drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source/drain pattern and the gate electrode to electrically connect the source/drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source/drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.

公开(公告)号：US20230187358A1

公开(公告)日：2023-06-15

申请号：US18077281

申请日：2022-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonyoung Jung ,  Deokhan Bae ,  Juhun Park ,  Yuri Lee ,  Sooyeon Hong

IPC: H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L23/535 ,  H01L27/0924 ,  H01L23/5283 ,  H01L29/7851 ,  H01L29/41791 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/66545 ,  H01L21/823821 ,  H01L21/823814 ,  H01L21/823871

Abstract: An integrated circuit device includes: a substrate including a device area and a field area; active regions extending in a first direction in the device area; a first gate structure extending in a second direction intersecting the first direction in the device area and the field area; a second gate structure spaced apart from the first gate structure in the first direction; a first gate contact disposed on the first gate structure in the device area; and a second gate contact disposed on the second gate structure in the field area, wherein the first gate contact and the second gate contact are disposed at a level lower than an upper end of the first gate structure, and wherein a first minimum width of the first gate contact and a second minimum width of the second gate contact are different from each other.

公开(公告)号：US11469298B2

公开(公告)日：2022-10-11

申请号：US17101703

申请日：2020-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhun Park ,  Deokhan Bae ,  Sungmin Kim ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L29/06 ,  H03K19/0185 ,  H01L27/092

Abstract: A semiconductor device includes a substrate having PMOSFET and NMOSFET regions spaced apart from each other in a direction, a device isolation layer provided on the substrate that defines first and second active patterns respectively on the PMOSFET and NMOSFET regions, a gate electrode crossing the first and second active patterns, first and second source/drain patterns respectively provided on the first and second active patterns respectively and near the gate electrode, and an active contact extending in the direction and coupled to the first and second source/drain patterns. The active contact includes first and second body portions, which are respectively provided on the first and the second source/drain patterns, and a first protruding portion and a recessed portion, which are provided between the first and second body portions and on the device isolation layer between the PMOSFET and NMOSFET regions. The recessed portion has an upwardly recessed bottom.

公开(公告)号：US20220320115A1

公开(公告)日：2022-10-06

申请号：US17538064

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source/drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source/drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source/drain pattern and the gate electrode to electrically connect the source/drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source/drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.

公开(公告)号：US12113109B2

公开(公告)日：2024-10-08

申请号：US17313638

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin Kim ,  Juhun Park ,  Deokhan Bae ,  Myungyoon Um ,  Yuri Lee ,  Inyeal Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L29/417 ,  H01L27/092

CPC classification number: H01L29/41791 ,  H01L27/0924

Abstract: A semiconductor device includes a first active (e.g., PMOSFET) region and an adjacent second active (e.g., NMOSFET) region on a substrate, a device isolation layer on the substrate and defining a first active pattern on the first active region and a second active pattern on the second active region, a gate electrode crossing the first and second active patterns, a first source/drain pattern and a second source/drain pattern adjacent to a side of the gate electrode, an interlayer insulating layer on the gate electrode, a first active contact penetrating the interlayer insulating layer to connect the first source/drain pattern and a second active contact penetrating the interlayer insulating layer to connect the second source/drain pattern and a buffer layer provided in an upper region of the interlayer insulating layer and interposed between the first active contact and the second active contact, wherein the buffer layer includes a material having etch selectivity with respect to the interlayer insulating layer.

公开(公告)号：US20240324165A1

公开(公告)日：2024-09-26

申请号：US18678213

申请日：2024-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source/drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source/drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source/drain pattern and the gate electrode to electrically connect the source/drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source/drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.

公开(公告)号：US11646316B2

公开(公告)日：2023-05-09

申请号：US17700590

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Sungmin Kim ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/6656 ,  H01L29/7851

Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

公开(公告)号：US20230120532A1

公开(公告)日：2023-04-20

申请号：US17717268

申请日：2022-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyeon Hong ,  Deokhan Bae ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device of the disclosure includes an active pattern extending on a substrate in a first direction, a gate structure extending on the active pattern in a second direction intersecting the first direction, a source/drain region disposed on at least one side of the gate structure, a source/drain contact connected to the source/drain region, and a contact insulating layer disposed on the source/drain contact. The contact insulating layer includes at least one air gap. The air gap is disposed on an upper surface of the source/drain contact.

公开(公告)号：US11217673B2

公开(公告)日：2022-01-04

申请号：US16874812

申请日：2020-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deokhan Bae ,  Sungmin Kim ,  Juhun Park ,  Yoonyoung Jung

IPC: H01L29/417 ,  H01L29/78 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L21/8238

Abstract: A semiconductor device including: a substrate including a first active region; a first active pattern on the first active region; a gate electrode intersecting the first active pattern and extending in a first direction; a first source/drain pattern on the first active pattern, the first source/drain pattern adjacent to the gate electrode; a first interlayer insulating layer covering the gate electrode and the first source/drain pattern; and an active contact penetrating the first interlayer insulating layer to be electrically connected to the first source/drain pattern, wherein the active contact extends in the first direction, wherein a top surface of the active contact includes: a first protrusion; a second protrusion; and a first depression between the first and second protrusions.

公开(公告)号：US10553593B2

公开(公告)日：2020-02-04

申请号：US15983405

申请日：2018-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Hyonwook Ra ,  Hyung Jong Lee ,  Juhun Park

IPC: H01L27/11 ,  H01L23/522 ,  G11C11/412 ,  H01L27/092

Abstract: A semiconductor device includes a substrate including active patterns, a device isolation layer filling a trench between a pair of adjacent active patterns, a gate electrode on the active patterns, and a gate contact on the gate electrode. Each active pattern includes source/drain patterns at opposite sides of the gate electrode. The gate contact includes a first portion vertically overlapping with the gate electrode, and a second portion laterally extending from the first portion such that the second portion vertically overlaps with the device isolation layer and does not vertically overlap with the gate electrode. A bottom surface of the second portion is distal to the substrate in relation to a bottom surface of the first portion. The bottom surface of the second portion is distal to the substrate in relation to a top of a source/drain pattern that is adjacent to the second portion.