公开(公告)号：US10903236B2

公开(公告)日：2021-01-26

申请号：US16663228

申请日：2019-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangyoon Choi ,  Dong-Sik Lee ,  Jongwon Kim ,  Gilsung Lee ,  Eunsuk Cho ,  Byungyong Choi ,  Sung-Min Hwang

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/04 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/02

Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.

公开(公告)号：US10861863B2

公开(公告)日：2020-12-08

申请号：US16235217

申请日：2018-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwon Kim ,  Minyeong Song

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11548 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565

Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer provided on a lower insulating layer. The horizontal semiconductor layer includes a cell array region and a connection region. An electrode structure is provided including electrodes. The electrodes are stacked on the horizontal semiconductor layer. The electrodes have a staircase structure on the connection region. A plurality of first vertical structures are provided on the cell array region to penetrate the electrode structure. A plurality of second vertical structures are provided on the connection region to penetrate the electrode structure and the horizontal semiconductor layer. Bottom surfaces of the second vertical structures are positioned at a level lower than a bottom surface of the horizontal semiconductor layer.

公开(公告)号：US20190035806A1

公开(公告)日：2019-01-31

申请号：US15955256

申请日：2018-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jongwon Kim ,  Dongseong Eun ,  Joonhee Lee

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11575

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

公开(公告)号：US11974438B2

公开(公告)日：2024-04-30

申请号：US17903315

申请日：2022-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haemin Lee ,  Jongwon Kim ,  Shinhwan Kang ,  Kohji Kanamori ,  Jeehoon Han

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/30 ,  H10B43/20

CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/30 ,  H10B43/20

Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.

公开(公告)号：US11733603B2

公开(公告)日：2023-08-22

申请号：US17180984

申请日：2021-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehoon Kim ,  Jaeho Jeong ,  Jeonghoon Ko ,  Jongwon Kim ,  Yejin Jeong ,  Changwook Jeong

IPC: G03F1/36 ,  H01L21/027 ,  G03F7/20 ,  G03F7/00

CPC classification number: G03F1/36 ,  G03F7/70441 ,  G03F7/70625 ,  H01L21/027

Abstract: A proximity correction method for a semiconductor manufacturing process includes: generating a plurality of pieces of original image data from a plurality of sample regions, with the sample regions selected from layout data used in the semiconductor manufacturing process; removing some pieces of original image data that overlap with each other from the plurality of pieces of original image data, resulting in a plurality of pieces of input image data; inputting the plurality of pieces of input image data to a machine learning model; obtaining a prediction value of critical dimensions of target patterns included in the plurality of pieces of input image data from the machine learning model; measuring a result value for critical dimensions of actual patterns corresponding to the target patterns on a semiconductor substrate on which the semiconductor manufacturing process is performed; and performing learning of the machine learning model using the prediction value and the result value.

公开(公告)号：US10818687B2

公开(公告)日：2020-10-27

申请号：US15991476

申请日：2018-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwon Kim ,  Young-Jin Jung

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11573 ,  H01L29/792

Abstract: A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.

公开(公告)号：US20200335520A1

公开(公告)日：2020-10-22

申请号：US16921185

申请日：2020-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jongwon Kim ,  Dongseog Eun ,  Joonhee Lee

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11575

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

公开(公告)号：US10685977B2

公开(公告)日：2020-06-16

申请号：US16231710

申请日：2018-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwon Kim ,  Hyeong Park ,  Hyunmin Lee ,  Hojong Kang ,  Joowon Park ,  Seungmin Song

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.