公开(公告)号：US11088148B2

公开(公告)日：2021-08-10

申请号：US16509820

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/792 ,  H01L21/71 ,  H01L21/8234

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US10748910B2

公开(公告)日：2020-08-18

申请号：US16053315

申请日：2018-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Sic Yoon ,  Dongoh Kim ,  Kiseok Lee ,  Sunghak Cho ,  Jemin Park

IPC: H01L27/108 ,  H01L21/762 ,  H01L21/311

Abstract: A semiconductor device includes a substrate that includes a cell region and a peripheral circuit region, a cell insulating pattern disposed in the cell region of the substrate that defines a cell active region, and a peripheral insulating pattern disposed in the peripheral circuit region of the substrate that defines a peripheral active region. The peripheral insulating pattern includes a first peripheral insulating pattern having a first width and a second peripheral insulating pattern having a second width greater than the first width. A topmost surface of at least one of the first peripheral insulating pattern and the second peripheral insulating pattern is positioned higher than a topmost surface of the cell insulating pattern.

公开(公告)号：US20180286870A1

公开(公告)日：2018-10-04

申请号：US15845141

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/792 ,  H01L21/28 ,  H01L21/71

CPC classification number: H01L27/10885 ,  H01L21/28273 ,  H01L21/71 ,  H01L21/823475 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10882 ,  H01L29/40114 ,  H01L29/7926

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US09929013B2

公开(公告)日：2018-03-27

申请号：US15402545

申请日：2017-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Yoosang Hwang

IPC: H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L27/11531 ,  H01L27/11575

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include etching a bulk pattern on a peripheral region to form patterns and then forming a layer on both a cell region and a peripheral region. The methods may include forming line patterns that extend from the cell region onto the peripheral region and then forming a layer on both the cell region and a peripheral region.

公开(公告)号：US20170200609A1

公开(公告)日：2017-07-13

申请号：US15402545

申请日：2017-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik KIM ,  Bong-Soo Kim ,  Jemin Park ,  Yoosang Hwang

IPC: H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L27/11531 ,  H01L27/11575

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include etching a bulk pattern on a peripheral region to form patterns and then forming a layer on both a cell region and a peripheral region. The methods may include forming line patterns that extend from the cell region onto the peripheral region and then forming a layer on both the cell region and a peripheral region.

公开(公告)号：US20200350319A1

公开(公告)日：2020-11-05

申请号：US16934874

申请日：2020-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHAN-SIC YOON ,  Dongoh Kim ,  Kiseok Lee ,  Sunghak Cho ,  Jemin Park

IPC: H01L27/108 ,  H01L21/762

Abstract: A semiconductor device includes a substrate that includes a cell region and a peripheral circuit region, a cell insulating pattern disposed in the cell region of the substrate that defines a cell active region, and a peripheral insulating pattern disposed in the peripheral circuit region of the substrate that defines a peripheral active region. The peripheral insulating pattern includes a first peripheral insulating pattern having a first width and a second peripheral insulating pattern having a second width greater than the first width. A topmost surface of at least one of the first peripheral insulating pattern and the second peripheral insulating pattern is positioned higher than a topmost surface of the cell insulating pattern.

公开(公告)号：US10410916B2

公开(公告)日：2019-09-10

申请号：US16106266

申请日：2018-08-21

Applicant: Samsung ELectronics Co., Ltd.

Inventor： Jiseok Hong ,  Kiseok Lee ,  Jemin Park ,  Yoosang Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes an interlayer insulation layer on a semiconductor substrate, a via plug and a wiring line on the via plug, in the interlayer insulation layer, the via plug and the wiring line coupled with each other and forming a stepped structure. The semiconductor device includes a first air-gap region between the interlayer insulation layer and the via plug, and a second air-gap region between the interlayer insulation layer and the wiring line. The first air-gap region and the second air-gap region are not vertically overlapped with each other.

公开(公告)号：US10037996B2

公开(公告)日：2018-07-31

申请号：US15646380

申请日：2017-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/00 ,  H01L27/108 ,  H01L21/3205 ,  H01L21/762 ,  H01L23/528 ,  H01L29/06 ,  H01L21/266 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L27/10814 ,  H01L21/266 ,  H01L21/3205 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/76224 ,  H01L23/5283 ,  H01L23/53257 ,  H01L23/53261 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/0649

Abstract: A semiconductor device includes a substrate, a bit line structure on the substrate, a first contact structure on a sidewall of the bit line structure, a second contact structure on the bit line structure and spaced apart from the first contact structure across the bit line structure, and an insulation pattern between the bit line structure and the first contact structure. The second contact structure covers at least a portion of a top surface of the bit line structure. The insulation pattern comprises a protrusion that protrudes from a sidewall of the insulation pattern that immediately adjacent to the bit line structure. The protrusion protrudes in a first direction parallel to a top surface of the substrate.

公开(公告)号：US20180096947A1

公开(公告)日：2018-04-05

申请号：US15608747

申请日：2017-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KISEOK LEE ,  Sooho Shin ,  Juik Lee ,  Jun Ho Lee ,  Kwangmin Kim ,  Ilyoung Moon ,  Jemin Park ,  Bumseok Seo ,  Chan-Sic Yoon ,  Hoin Lee

IPC: H01L23/544 ,  H01L27/108

CPC classification number: H01L23/544 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

公开(公告)号：US09831172B2

公开(公告)日：2017-11-28

申请号：US14971402

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Jemin Park ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L21/02 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10897 ,  H01L29/4236 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in a substrate, a recess region exposing an upper surface of the first active region and upper surfaces of the first and second device isolation regions, and active buffer patterns on the second and third active regions. The first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions. Upper sidewalls of the second and third active regions are exposed in the recess region.