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公开(公告)号：US20240244832A1
公开(公告)日：2024-07-18
申请号：US18378191
申请日：2023-10-10
发明人： Kiseok Lee , Keunnam Kim , Hui-Jung Kim
IPC分类号： H10B12/00
CPC分类号： H10B12/488 , H10B12/482 , H10B12/485
摘要： A semiconductor device including: a device isolation part on a substrate to define first to fourth active regions, the device isolation part interposed between the first and second active regions and the third and fourth active regions; first and second word lines crossing the first and second active regions and adjacent to each other; a first impurity region in the first active region between the first and second word lines; a second impurity region in the first active region at one side of the first word line and spaced apart from the first impurity region; a first conductive pad contacting the first impurity region; a second conductive pad contacting the second impurity region; a bit line on the first conductive pad; a storage node contact on the second conductive pad; and a landing pad on the storage node contact.
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公开(公告)号：US20240213071A1
公开(公告)日：2024-06-27
申请号：US18396553
申请日：2023-12-26
发明人： Junho IM , Younseon Wang , Yongwoo Kim , Taehwa Kim , Inseok Seo , Kiseok Lee
IPC分类号： H01L21/683 , H01J37/32
CPC分类号： H01L21/6833 , H01J37/32715
摘要： An electrostatic chuck includes an electrostatic chuck body having a step portion protruding from a lower end, an adhesive layer disposed on an upper surface of the electrostatic chuck body, a ceramic puck adhered to the adhesive layer and having an edge protruding from the upper surface of the electrostatic chuck body, and a sealant disposed between the step portion and the edge of the ceramic puck and configured to block reaction gas from permeating into the adhesive layer. The sealant includes a coating layer disposed on an external surface thereof, and the coating layer includes a metal oxide including a single rare earth oxide and/or a multilayer heterogeneous metal oxide.
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公开(公告)号：US20240172428A1
公开(公告)日：2024-05-23
申请号：US18518293
申请日：2023-11-22
发明人： KYUNGHWAN KIM , Hyungeun Choi , Keunnam Kim , Seokhan Park , Seokho Shin , Joongchan Shin , Kiseok Lee , Sangho Lee , Moonyoung Jeong
IPC分类号： H10B12/00
CPC分类号： H10B12/50 , H10B12/09 , H10B12/315
摘要： A semiconductor device is provided. The semiconductor device includes: a lower structure including a bit line; a cell semiconductor body vertically overlapping the bit line, on the lower structure; a peripheral semiconductor body including a portion disposed on a same level as at least a portion of the cell semiconductor body, on the lower structure; and a peripheral gate on the peripheral semiconductor body, wherein the peripheral semiconductor body includes a lower region having a first width and an upper region having a second width, greater than the first width on the lower region.
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公开(公告)号：US20230413538A1
公开(公告)日：2023-12-21
申请号：US18148566
申请日：2022-12-30
发明人： Hyeran Lee , Junhyeok Ahn , Kiseok Lee
IPC分类号： H10B12/00 , H01L29/423 , H01L23/528
CPC分类号： H10B12/488 , H01L23/5283 , H10B12/482 , H01L29/4236
摘要： An integrated circuit device includes a substrate comprising an active region and a word line trench, a word line extending longitudinally in a first horizontal direction in the word line trench, a buried insulating layer on the word line, a conductive plug on the substrate, and a pad structure on the substrate and having a portion in contact with a top surface of the active region and a portion in contact with the conductive plug. The pad structure includes a conductive pad having a bottom surface in contact with the top surface of the active region and a pad spacer in contact with a sidewall of the conductive pad and protruding beyond an inner sidewall of the word line trench in a second horizontal direction orthogonal to the first horizontal direction such that the pad spacer vertically overlaps a portion of the word line in the word line trench.
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公开(公告)号：US20230354582A1
公开(公告)日：2023-11-02
申请号：US18062825
申请日：2022-12-07
发明人： Kiseok Lee , Byeongjoo Ku , Keunnam Kim , Wonsok Lee , Moonyoung Jeong , Min Hee Cho
IPC分类号： H01L29/94
CPC分类号： H10B12/315 , H10B12/05
摘要： A semiconductor device may include a bit line extending in a first direction, a semiconductor pattern on the bit line, the semiconductor pattern including first and second vertical portions, which are opposite to each other in the first direction, and a horizontal portion connecting the first and second vertical portions, first and second word lines on the horizontal portion to be adjacent to the first and second vertical portions, respectively, and a gate insulating pattern between the first vertical portion and the first word line and between the second vertical portion and the second word line. A bottom surface of the horizontal portion may be located at a height that is lower than or equal to the uppermost surface of the bit line.
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公开(公告)号：US20230320077A1
公开(公告)日：2023-10-05
申请号：US18187229
申请日：2023-03-21
发明人： Moonyoung Jeong , Kiseok Lee , Sangho Lee , Hyungjun Noh
IPC分类号： H10B12/00 , H01L23/528
CPC分类号： H10B12/36 , H10B12/482 , H10B12/488 , H01L23/5283 , H10B12/485
摘要： A semiconductor device includes a substrate, a first gate structure and a second gate structure on the substrate, a single back gate structure between the first gate structure and the second gate structure, a first structure including a first vertical channel region extending in a vertical direction, at least a portion of the first vertical channel region between the first gate structure and the single back gate structure, and a second structure including a second vertical channel region extending in the vertical direction. The second structure is spaced apart from the first structure, and at least a portion of the second vertical channel region is between the second gate structure and the single back gate structure.
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公开(公告)号：US11696434B2
公开(公告)日：2023-07-04
申请号：US17241860
申请日：2021-04-27
发明人： Kiseok Lee , Kyunghwan Lee , Dongoh Kim , Yongseok Kim , Hui-Jung Kim , Min Hee Cho
IPC分类号： H10B12/00
CPC分类号： H10B12/315 , H10B12/395 , H10B12/50
摘要： A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.
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公开(公告)号：US11647627B2
公开(公告)日：2023-05-09
申请号：US17168952
申请日：2021-02-05
发明人： Jiseok Hong , Sangho Lee , Seoryong Park , Jiyoung Ahn , Kiseok Lee , Kiseok Lee , Yoonyoung Choi , Seunguk Han
IPC分类号： H01L27/108
CPC分类号： H01L27/10888 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.
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公开(公告)号：US11616065B2
公开(公告)日：2023-03-28
申请号：US17090419
申请日：2020-11-05
发明人： Jiyoung Kim , Kiseok Lee , Bong-Soo Kim , Junsoo Kim , Dongsoo Woo , Kyupil Lee , HyeongSun Hong , Yoosang Hwang
IPC分类号： H01L27/108 , H01L27/06 , H01L49/02
摘要： Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.
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公开(公告)号：US11521977B2
公开(公告)日：2022-12-06
申请号：US17471824
申请日：2021-09-10
发明人： Kiseok Lee , Chan-Sic Yoon , Augustin Hong , Keunnam Kim , Dongoh Kim , Bong-Soo Kim , Jemin Park , Hoin Lee , Sungho Jang , Kiwook Jung , Yoosang Hwang
IPC分类号： H01L27/108 , H01L27/24 , H01L27/22
摘要： A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.
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