公开(公告)号：US20230120532A1

公开(公告)日：2023-04-20

申请号：US17717268

申请日：2022-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyeon Hong ,  Deokhan Bae ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device of the disclosure includes an active pattern extending on a substrate in a first direction, a gate structure extending on the active pattern in a second direction intersecting the first direction, a source/drain region disposed on at least one side of the gate structure, a source/drain contact connected to the source/drain region, and a contact insulating layer disposed on the source/drain contact. The contact insulating layer includes at least one air gap. The air gap is disposed on an upper surface of the source/drain contact.

公开(公告)号：US11217673B2

公开(公告)日：2022-01-04

申请号：US16874812

申请日：2020-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deokhan Bae ,  Sungmin Kim ,  Juhun Park ,  Yoonyoung Jung

IPC: H01L29/417 ,  H01L29/78 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L21/8238

Abstract: A semiconductor device including: a substrate including a first active region; a first active pattern on the first active region; a gate electrode intersecting the first active pattern and extending in a first direction; a first source/drain pattern on the first active pattern, the first source/drain pattern adjacent to the gate electrode; a first interlayer insulating layer covering the gate electrode and the first source/drain pattern; and an active contact penetrating the first interlayer insulating layer to be electrically connected to the first source/drain pattern, wherein the active contact extends in the first direction, wherein a top surface of the active contact includes: a first protrusion; a second protrusion; and a first depression between the first and second protrusions.

公开(公告)号：US10553593B2

公开(公告)日：2020-02-04

申请号：US15983405

申请日：2018-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Hyonwook Ra ,  Hyung Jong Lee ,  Juhun Park

IPC: H01L27/11 ,  H01L23/522 ,  G11C11/412 ,  H01L27/092

Abstract: A semiconductor device includes a substrate including active patterns, a device isolation layer filling a trench between a pair of adjacent active patterns, a gate electrode on the active patterns, and a gate contact on the gate electrode. Each active pattern includes source/drain patterns at opposite sides of the gate electrode. The gate contact includes a first portion vertically overlapping with the gate electrode, and a second portion laterally extending from the first portion such that the second portion vertically overlaps with the device isolation layer and does not vertically overlap with the gate electrode. A bottom surface of the second portion is distal to the substrate in relation to a bottom surface of the first portion. The bottom surface of the second portion is distal to the substrate in relation to a top of a source/drain pattern that is adjacent to the second portion.

公开(公告)号：US11757040B2

公开(公告)日：2023-09-12

申请号：US17569952

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deokhan Bae ,  Juhun Park ,  Myungyoon Um ,  Kwangyong Jang

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41725 ,  H01L29/66545

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction.

公开(公告)号：US11575044B2

公开(公告)日：2023-02-07

申请号：US17179982

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Juhun Park ,  Myungyoon Um

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8238

Abstract: An integrated circuit device includes a substrate including first and second fin-type active areas, a gate structure on the first and second fin-type active areas, first and second source/drain regions on the first and second fin-type active areas, respectively, a first source/drain contact on the first source/drain region and comprising first and second portions, a second source/drain contact on the second source/drain region and comprising first and second portions, the second portion having an upper surface at a lower level than an upper surface of the first portion, a first stressor layer on the upper surface of the second portion of the first source/drain contact, and a second stressor layer on the upper surface of the second portion of the second source/drain contact, the second stressor layer including a material different from a material included in the first stressor layer.

公开(公告)号：US11251306B2

公开(公告)日：2022-02-15

申请号：US17028191

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deokhan Bae ,  Juhun Park ,  Myungyoon Um ,  Kwangyong Jang

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction.

公开(公告)号：US20210384192A1

公开(公告)日：2021-12-09

申请号：US17179469

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Sungmin Kim ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

公开(公告)号：US10910387B2

公开(公告)日：2021-02-02

申请号：US16374363

申请日：2019-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyoung Kim ,  Hyung Jong Lee ,  Deokhan Bae

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

Abstract: Disclosed is a semiconductor device including a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction, a first gate structure that extends across the first and second active patterns, a second gate structure that is spaced apart from the first gate structure, and a node contact between the first and second gate structures that electrically connects the first active pattern and the second active pattern to each other. The node contact comprises a first end adjacent to the first active pattern and a second end adjacent to the second active pattern. The second end of the node contact being shifted in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.

公开(公告)号：US20190252372A1

公开(公告)日：2019-08-15

申请号：US16395593

申请日：2019-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwichan Jun ,  Deokhan Bae ,  HeonJong Shin ,  Jaeran Jang ,  Moon Gi Cho ,  YoungWoo Cho

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/32139 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L27/0924 ,  H01L28/20 ,  H01L29/0696 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.

公开(公告)号：US12288749B2

公开(公告)日：2025-04-29

申请号：US18647307

申请日：2024-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inyeal Lee ,  Dongbeen Kim ,  Jinwook Kim ,  Juhun Park ,  Deokhan Bae ,  Junghoon Seo ,  Myungyoon Um

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A circuit chip including a substrate, first and second channel active regions on the substrate, and extending in a first direction, the second channel active regions spaced apart from the first channel regions in a second direction intersecting the first direction, first and second gate electrodes intersecting the second channel active regions, third and fourth gate electrodes intersecting the first channel active regions, and a contact electrode between the first, second, third, and fourth gate electrodes. The contact electrode including a stem section in a vertical direction, and first and second branch sections extending from the stem section and contacting a respective source/drain region on the first and second channel active regions, the first gate electrode and the third gate electrode overlapping in the second direction, and including edge portions having widths decreasing as the first gate electrode and the third gate electrode extend toward facing ends thereof.