公开(公告)号：US20230094036A1

公开(公告)日：2023-03-30

申请号：US17838551

申请日：2022-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Panjae Park ,  Subin Choi ,  Chulhong Park

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction, a gate electrode intersecting the active region and extending in a second direction, perpendicular to the first direction, a contact structure disposed on the active region on one side of the gate electrode and extending in the second direction, and a first via disposed on the contact structure to be connected to the contact structure and has a shape in which a length in the second direction is greater than a length in the first direction. A plurality of first metal interconnections are provided, which extend in the first direction on the first via, and are connected to the first via. A second via is provided, which is disposed on the plurality of first metal interconnections to be connected to the plurality of first metal interconnections and has a shape in which a length in the second direction is greater than a length in the first direction.

公开(公告)号：US20170309627A1

公开(公告)日：2017-10-26

申请号：US15641417

申请日：2017-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel AZMAT ,  Sharma Deepak ,  Chulhong Park

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/118

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0847 ,  H01L2027/11829 ,  H01L2027/11875

Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.

公开(公告)号：US09748238B2

公开(公告)日：2017-08-29

申请号：US15206610

申请日：2016-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sharma Deepak ,  Chulhong Park

IPC: H01L27/08 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L27/118 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0847 ,  H01L2027/11829 ,  H01L2027/11875

Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.