知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

53 records (took 0.082 seconds)

    Semiconductor devices and methods of manufacturing the same
    12.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权

    公开(公告)号：US11411004B2

    公开(公告)日：2022-08-09

    申请号：US16903040

    申请日：2020-06-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

    IPC: H01L27/108

    Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

    Semiconductor device having dual metal silicide layers and method of manufacturing the same
    16.
    发明授权
    Semiconductor device having dual metal silicide layers and method of manufacturing the same 有权
    具有双金属硅化物层的半导体器件及其制造方法

    公开(公告)号：US09117692B2

    公开(公告)日：2015-08-25

    申请号：US14513807

    申请日：2014-10-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Byung-Kwon Cho ,  Wonsang Choi

    IPC: H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51

    CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/161 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

    Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

    Abstract translation: 使用双金属硅化物层制造半导体器件。 半导体器件包括具有第一和第二区域的衬底，第一区域中的衬底上的第一金属栅电极，第二区域中的衬底上的第二金属栅电极，两侧的衬底上的第一外延层 的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层， 在第一和第二金属硅化物层上的电介质层，通过层间电介质层并电连接到第一和第二金属硅化物层的接触插塞。

    METHODS OF FABRICATING A SEMICONDUCTOR DEVICE
    17.
    发明申请
    METHODS OF FABRICATING A SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20140051246A1

    公开(公告)日：2014-02-20

    申请号：US13962479

    申请日：2013-08-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chae Lyoung Kim ,  Ilyoung Yoon ,  Boun Yoon

    IPC: H01L21/306

    CPC classification number: H01L21/30625 ,  H01L21/3212 ,  H01L21/7684 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of fabricating a semiconductor device are provided. The methods may include preparing a semiconductor substrate, forming insulating patterns including a trench on the semiconductor substrate, conformally forming a metal layer covering an inner surface of the trench on the insulating patterns, conformally forming a protecting layer on the metal layer, and performing a chemical mechanical polishing (CMP) process on the protecting layer and the metal layer until top surfaces of the insulating patterns are exposed, thereby forming a metal pattern and a protecting pattern in the trench. The CMP process may use a slurry including polishing particles having negative charges.

    Abstract translation: 提供制造半导体器件的方法。 所述方法可以包括制备半导体衬底，在半导体衬底上形成包括沟槽的绝缘图案，保形地形成覆盖绝缘图案上的沟槽的内表面的金属层，在金属层上保形地形成保护层，并执行 在保护层和金属层上的化学机械抛光（CMP）工艺直到绝缘图案的顶表面露出，从而在沟槽中形成金属图案和保护图案。 CMP工艺可以使用包含具有负电荷的抛光颗粒的浆料。

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    19.
    发明公开
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240155830A1

    公开(公告)日：2024-05-09

    申请号：US18413434

    申请日：2024-01-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

    IPC: H10B12/00

    CPC classification number: H10B12/37 ,  H10B12/0387 ,  H10B12/482 ,  H10B12/50

    Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

    Semiconductor devices and methods of manufacturing the same
    20.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权

    公开(公告)号：US11910594B2

    公开(公告)日：2024-02-20

    申请号：US17859247

    申请日：2022-07-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

    IPC: H10B12/00

    CPC classification number: H10B12/37 ,  H10B12/0387 ,  H10B12/482 ,  H10B12/50

    Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

Patent Agency Ranking