公开(公告)号：US20240311082A1

公开(公告)日：2024-09-19

申请号：US18194894

申请日：2023-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saurabh Shankar ZOND ,  Debojyoti Banerjee ,  Abhishek Ghosh ,  Raghavendra Shirodkar ,  Rakesh Dimri ,  Yashaswini H G

IPC: G06F7/501 ,  H03K19/20 ,  H03K19/21

CPC classification number: G06F7/501 ,  H03K19/20 ,  H03K19/215

Abstract: Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder (FA) circuit. The FA circuit comprises a sum generation circuit configured to generate a sum output and a carry output generation circuit configured to generate a carry output. The sum generation circuit comprises a first exclusive-NOR gate and a second exclusive-NOR gate. The carry output generation circuit comprises a first or-and-invert (OAI) gate, a second OAI gate, and a NAND gate. The first OAI gate is configured to receive an output of the NAND gate to generate one of an exclusive-NOR output or a NOR output of a first operand and a second operand. The second OAI gate is configured to receive the output of the NAND gate, an inverse of a carry input, and the generated one of the exclusive-NOR output or the NOR output to produce the carry output.

公开(公告)号：US20230418556A1

公开(公告)日：2023-12-28

申请号：US17821763

申请日：2022-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Debojyoti Banerjee ,  Abhishek Ghosh ,  Raghavendra Ramakant Shirodkar ,  Rakesh Dimri ,  Utkarsh Garg

IPC: G06F7/501 ,  H03K19/20 ,  H03K17/687

CPC classification number: G06F7/501 ,  H03K19/20 ,  H03K17/6872

Abstract: Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder circuit. The integrated circuit includes a carry generation circuit configured to receive a first input and a second input to generate a carry, and a carry propagation circuit configured to receive the first input, the second input, and a third input to generate a propagated output. The integrated circuit further includes a carry output generation circuit configured to receive the generated carry and the propagated output to generate a final carry as an output, and a sum generation circuit configured to generate a sum output. The sum generation circuit includes the carry generation circuit and is configured to receive the first input, the second input, and generated carry to generate an exclusive NOR output, and further uses the generated exclusive NOR output and the third input to generate the sum output.

公开(公告)号：US11569799B2

公开(公告)日：2023-01-31

申请号：US17188510

申请日：2021-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Aroma Bhat ,  Arani Roy ,  Mitesh Goyal ,  Abhishek Ghosh

IPC: H03K3/3562 ,  H03K3/037

Abstract: A True Single-Phase Clock (TSPC) NAND-based reset flip-flop includes a reset functionality to perform a reset operation. The flip-flop with the reset functionality includes a master section and a slave section. The reset functionality is achieved using two transistors in the master section. The master section and the slave section operate using the TSPC. The master section and the slave section may include a plurality of NAND circuits and a NAND and NOR circuit for performing the reset operation. The master section outputs a plurality of internal signals on receiving a data input, a scan enable signal, a scan input signal, a reset control signal, and a clock signal. The slave section generates an output on receiving the plurality of internal signals received from the master section.

公开(公告)号：US11366161B2

公开(公告)日：2022-06-21

申请号：US17117544

申请日：2020-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Arani Roy ,  Arava Prakash ,  Aroma Bhat ,  Mitesh Goyal ,  Abhishek Ghosh

IPC: G01R31/3177 ,  G01R31/317 ,  H03K3/037

Abstract: A True Single Phase Clock (TSPC) pre-charge based flip-flop is provided. The flip-flop includes a scan section, a master section, and a slave section. The scan section receives a scan enable signal, a scan input signal, a clock signal, and feedback data from the master section, and outputs an internal signal to the master section based on the scan enable signal, the scan input signal, the clock signal, and the feedback data. The master section is coupled to the scan section and receives the internal signal and a data input, and outputs a master feedback signal to the slave section based on the internal signal, the data input, and the feedback data. The slave section is coupled to the master section and generates an output by latching the master feedback signal received from the master section according to the clock signal. The clock signal is a True-Single-Phase-Clock (TSPC).

公开(公告)号：US11362648B2

公开(公告)日：2022-06-14

申请号：US17118082

申请日：2020-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aroma Bhat ,  Abdur Rakheeb ,  Arani Roy ,  Mitesh Goyal ,  Abhishek Ghosh

IPC: H03K3/3562 ,  G01R31/3177 ,  H03K3/027 ,  H03K3/012

Abstract: A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.

公开(公告)号：US20210167781A1

公开(公告)日：2021-06-03

申请号：US16807640

申请日：2020-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hareharan Nagarajan ,  Abhishek Ghosh ,  Sajal Mittal

IPC: H03K19/21 ,  H03K19/0948

Abstract: A CMOS transistor circuit including: a first block generating a first output signal of a NOR state, in response to first and second input signals; a second block including a first AND-OR gate, the second block generating a second output signal of an OR or an AND state, the second block receiving the first and second input signals and the first output signal; a third block generating a third output signal of the NOR state, in response to a third input signal and the second output signal; a fourth block including a second AND-OR gate, the fourth block generating a fourth output signal of the OR or the AND state in response to the third input signal, the second output signal and the third output signal; and a fifth block including an inverter gate, the fifth block generating a fifth output signal in response to the fourth output signal.

公开(公告)号：US10672756B2

公开(公告)日：2020-06-02

申请号：US16238009

申请日：2019-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sajal Mittal ,  Abhishek Ghosh ,  Utkarsh Garg

IPC: G06F7/50 ,  H01L27/02 ,  H03K19/0185 ,  G06F30/392 ,  H01L27/118

Abstract: Example embodiments provides a full adder integrated circuit (ADDF) for improving area and power of an integrated circuit (IC). The method includes receiving three input signals and generating three corresponding complementary output signals. Further, the method includes generating an internal signal using two complementary output signals out of the generated three corresponding complementary output signals, and one of the three input signals. Further, the method includes generating an output summation signal using a complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and a complementary internal signal of the generated internal signal. Further, the method includes generating a carry-out signal using two complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and the complementary internal signal. Example embodiments herein also provide a four input multiplexer Integrated circuit (MXT4) for reducing the area of the IC.

公开(公告)号：US10651850B2

公开(公告)日：2020-05-12

申请号：US16363292

申请日：2019-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sajal Mittal ,  Jaskaran Singh Bhatia ,  Rajeela Deshpande ,  Parvinder Kumar Rana ,  Nikhila C M ,  Abhishek Ghosh ,  Rahul Kataria

IPC: H03K19/00 ,  H03K19/0185 ,  H03K3/012 ,  H03K3/037

Abstract: A method and a flip-flop for designing low power integrated circuits (IC's). The method includes receiving at least one of a clock signal, a data signal, and a complimentary data signal. The complimentary data signal is produced by an input data inverter present in the flip-flop. Further, the method includes generating at least one master internal signal based on the received at least one of the clock signal, the data signal, and the complimentary data signal, when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal, when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one slave internal signal.

公开(公告)号：US20200136594A1

公开(公告)日：2020-04-30

申请号：US16661205

申请日：2019-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sajal Mittal ,  Aroma Bhat ,  Hareharan Nagarajan ,  Rahul Kataria ,  Abhishek Ghosh

IPC: H03K3/037

Abstract: Embodiments herein disclose a flip flop comprising at least one of a slave circuit and a retention circuit receiving an input from a master circuit. The output circuit receives an input (X1) from at least one of the slave circuit and the retention circuit. A first node and a second node in the retention circuit receive a power supply from a global power supply through transistors, when a retention is 0 in the retention circuit, so that the slave circuit retains a current state of the X1 and X2 irrespective of a clock input in the slave circuit, and the output circuit receives the stored state of the retention circuit, when a local power supply is turned ON.

公开(公告)号：US20190006388A1

公开(公告)日：2019-01-03

申请号：US16124946

申请日：2018-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam Agarwal ,  Abhishek Ghosh ,  Parvinder Kumar Rana

IPC: H01L27/118

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.