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    Thin film transistor and method of forming the same
    15.
    发明授权
    Thin film transistor and method of forming the same 有权
    薄膜晶体管及其形成方法

    公开(公告)号：US09406785B2

    公开(公告)日：2016-08-02

    申请号：US14521043

    申请日：2014-10-22

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Doo Hyoung Lee ,  Bo Sung Kim ,  Chan Woo Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

    IPC: H01L21/441 ,  H01L21/02 ,  H01L21/385 ,  H01L29/66 ,  H01L29/786 ,  H01L21/477

    CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

    Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

    Abstract translation: 薄膜晶体管包括衬底，设置在衬底上的氧化物半导体层，与氧化物半导体层重叠的栅电极，设置在氧化物半导体层和栅电极之间的栅极绝缘层，以及源极 电极和与氧化物半导体层至少部分重叠并且彼此间隔开的漏电极。 栅极绝缘层包括包含第一材料的氧化物。 氧化物半导体层包括与第一材料相同的材料和第二材料的氧化物，源电极和漏极包括包含与第二材料相同的材料的氧化物和第三材料，以及晶界 不形成在栅极绝缘层和氧化物半导体层中的至少一个之间或氧化物半导体层以及源电极和漏电极之间的界面上。

    Thin film transistor and method of forming the same
    16.
    发明授权
    Thin film transistor and method of forming the same 有权
    薄膜晶体管及其形成方法

    公开(公告)号：US08895977B2

    公开(公告)日：2014-11-25

    申请号：US13673195

    申请日：2012-11-09

    Applicant: Samsung Display Co., Ltd.

    Inventor： Doo Hyoung Lee ,  Bo Sung Kim ,  Chan Woo Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

    IPC: H01L21/786 ,  H01L29/786 ,  H01L21/385

    CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

    Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

    Abstract translation: 薄膜晶体管包括衬底，设置在衬底上的氧化物半导体层，与氧化物半导体层重叠的栅电极，设置在氧化物半导体层和栅电极之间的栅极绝缘层，以及源极 电极和与氧化物半导体层至少部分重叠并且彼此间隔开的漏电极。 栅极绝缘层包括包含第一材料的氧化物。 氧化物半导体层包括与第一材料相同的材料和第二材料的氧化物，源电极和漏极包括包含与第二材料相同的材料的氧化物和第三材料，以及晶界 不形成在栅极绝缘层和氧化物半导体层中的至少一个之间或氧化物半导体层以及源电极和漏电极之间的界面上。

    Precursor composition of oxide semiconductor and thin film transistor substrate including oxide semiconductor
    17.
    发明授权
    Precursor composition of oxide semiconductor and thin film transistor substrate including oxide semiconductor 有权
    包含氧化物半导体的氧化物半导体和薄膜晶体管衬底的前体组成

    公开(公告)号：US08853687B2

    公开(公告)日：2014-10-07

    申请号：US13679910

    申请日：2012-11-16

    Applicant: Samsung Display Co., Ltd.

    Inventor： Doo Hyoung Lee ,  Chan Woo Yang ,  Seung-Ho Jung ,  Doo Na Kim ,  Bo Sung Kim ,  Eun Hye Park

    IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L29/66 ,  H01B1/06

    CPC classification number: H01L29/66969 ,  H01B1/06 ,  H01L21/02565 ,  H01L21/02628 ,  H01L29/7869

    Abstract: A thin film transistor substrate according to an exemplary embodiment of the present invention includes a semiconductor layer including metal disposed on an insulating substrate, a gate electrode overlapping the semiconductor layer, and a source electrode and a drain electrode overlapping the semiconductor layer, wherein the metal in the semiconductor layer comprises indium (In), zinc (Zn), and tin (Sn), and a molar ratio ( R , R ⁡ [ mol ⁢ ⁢ % ] = [ In ] [ In + Zn + Sn ] × 100 ) of indium (In) to the metals in the semiconductor layer is less than about 20%, and more specifically, the molar ratio (R, ( R , R ⁡ [ mol ⁢ ⁢ % ] = [ In ] [ In + Zn + Sn ] / 100 ) of indium (In) of the metals in the semiconductor layer is about 5% to about 13%.

    Abstract translation: 根据本发明的示例性实施例的薄膜晶体管基板包括：半导体层，包括设置在绝缘基板上的金属，与半导体层重叠的栅极电极以及与半导体层重叠的源电极和漏电极，其中金属 在半导体层中包含铟（In），锌（Zn）和锡（Sn），摩尔比（R，R⁡[mol⁢％] = [In] [In + Zn + Sn]×100） 对于半导体层中的金属，铟（In）的含量小于约20％，更具体地，摩尔比（R，（R，R⁡[mol⁢％] = [In] [In + Zn + Sn 半导体层中的金属的In（In）的比例为约5％〜13％。

    THIN FILM TRANSISTOR AND METHOD OF FORMING THE SAME
    18.
    发明申请
    THIN FILM TRANSISTOR AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20130320327A1

    公开(公告)日：2013-12-05

    申请号：US13673195

    申请日：2012-11-09

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Doo Hyoung LEE ,  Bo Sung Kim ,  Chan Woo Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

    IPC: H01L29/786 ,  H01L21/385

    CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

    Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

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