公开(公告)号：US09524992B2

公开(公告)日：2016-12-20

申请号：US14875320

申请日：2015-10-05

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hye Young Ryu ,  Hee Jun Byeon ,  Woo Geun Lee ,  Kap Soo Yoon ,  Yoon Ho Kim ,  Chun Won Byun

IPC: G02F1/1362 ,  H01L27/12 ,  G02F1/1343 ,  G02F1/1368

CPC classification number: H01L27/127 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2001/136295 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262

Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.

公开(公告)号：US11943976B2

公开(公告)日：2024-03-26

申请号：US16892988

申请日：2020-06-04

Applicant: Samsung Display Co., LTD.

Inventor： Seung Sok Son ,  Woo Geun Lee ,  Seul Ki Kim ,  Kap Soo Yoon ,  Hyun Woong Baek ,  Jae Hyun Lee ,  Su Jung Jung ,  Jung Kyoung Cho ,  Seung Ha Choi ,  June Whan Choi

IPC: G02F1/1362 ,  G09G3/32 ,  H10K59/121 ,  H10K59/131 ,  H10K59/38 ,  H10K59/12

CPC classification number: H10K59/131 ,  G09G3/32 ,  G09G2300/0426 ,  G09G2310/0202 ,  H10K59/1201

Abstract: A display device includes a substrate, a first conductive layer on the substrate, the first conductive layer including a data signal line, a first insulating layer on the first conductive layer, a semiconductor layer on the first insulating layer, the semiconductor layer including a first semiconductor pattern, a second insulating layer on the semiconductor layer, and a second conductive layer on the second insulating layer, the second conductive layer including a gate electrode disposed to overlap the first semiconductor pattern, a transistor first electrode disposed to overlap a part of the first semiconductor pattern, wherein the transistor first electrode is electrically connected to the data signal line through a contact hole that penetrates the first and second insulating layers, and a transistor second electrode disposed to overlap another part of the first semiconductor pattern.

公开(公告)号：US11127339B2

公开(公告)日：2021-09-21

申请号：US16875682

申请日：2020-05-15

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam Kim ,  Sung Hoon Lim ,  Woo Geun Lee ,  Kyu Sik Cho ,  Jae Beom Choi

IPC: G09G3/3266 ,  G09G3/20

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US09012994B2

公开(公告)日：2015-04-21

申请号：US14012580

申请日：2013-08-28

Applicant: Samsung Display Co., Ltd.

Inventor： Seung-Ho Jung ,  Young Joo Choi ,  Joon Geol Kim ,  Kang Moon Jo ,  Sho Yeon Kim ,  Byung Hwan Chu ,  Woo Geun Lee ,  Woo-Seok Jeon

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L27/1288

Abstract: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.

Abstract translation: 公开了薄膜晶体管阵列面板。 薄膜晶体管阵列面板可以包括设置在基板上并包括栅电极的栅极线，包括设置在基板上的氧化物半导体的半导体层，设置在基板上的数据布线层，并且包括与栅极线交叉的数据线 连接到数据线的源电极和面对源电极的漏电极，覆盖源电极和漏电极的聚合物层和设置在聚合物层上的钝化层。 数据布线层可以包括铜或铜合金，并且聚合物层可以包括碳氟化合物。