公开(公告)号：US11127339B2

公开(公告)日：2021-09-21

申请号：US16875682

申请日：2020-05-15

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam Kim ,  Sung Hoon Lim ,  Woo Geun Lee ,  Kyu Sik Cho ,  Jae Beom Choi

IPC: G09G3/3266 ,  G09G3/20

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US11626060B2

公开(公告)日：2023-04-11

申请号：US17478825

申请日：2021-09-17

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam Kim ,  Sung Hoon Lim ,  Woo Geun Lee ,  Kyu Sik Cho ,  Jae Beom Choi

IPC: G09G3/3266 ,  G09G3/20

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US12002404B2

公开(公告)日：2024-06-04

申请号：US18132704

申请日：2023-04-10

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam Kim ,  Sung Hoon Lim ,  Woo Geun Lee ,  Kyu Sik Cho ,  Jae Beom Choi

IPC: G09G3/20 ,  G09G3/3266 ,  G09G3/3233

CPC classification number: G09G3/2092 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2310/0202 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/08

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US11521570B2

公开(公告)日：2022-12-06

申请号：US16809452

申请日：2020-03-04

Applicant: Samsung Display Co., Ltd.

Inventor： Sung Hoon Lim ,  Kang Nam Kim ,  Seok Hwan Bang ,  Sung Hwan Won ,  Woo Geun Lee ,  Kyu Sik Cho ,  Soo Jung Chae

IPC: G09G3/36

Abstract: A gate driver for a display device includes: a clock signal line to transfer a clock signal; and a plurality of stages to sequentially output a gate signal based upon the clock signal in response to a carry signal. The plurality of stages include a plurality of thin film transistors, and at least one of the plurality of thin film transistors includes a thin film transistor including an oxide semiconductor. The at least one thin film transistor includes a first gate electrode and a second gate electrode disposed in different layers, the oxide semiconductor is disposed between the first gate electrode and the second gate electrode, and the first gate electrode and the second gate electrode are connected to receive a common voltage signal.