公开(公告)号：US11521570B2

公开(公告)日：2022-12-06

申请号：US16809452

申请日：2020-03-04

Applicant: Samsung Display Co., Ltd.

Inventor： Sung Hoon Lim ,  Kang Nam Kim ,  Seok Hwan Bang ,  Sung Hwan Won ,  Woo Geun Lee ,  Kyu Sik Cho ,  Soo Jung Chae

IPC: G09G3/36

Abstract: A gate driver for a display device includes: a clock signal line to transfer a clock signal; and a plurality of stages to sequentially output a gate signal based upon the clock signal in response to a carry signal. The plurality of stages include a plurality of thin film transistors, and at least one of the plurality of thin film transistors includes a thin film transistor including an oxide semiconductor. The at least one thin film transistor includes a first gate electrode and a second gate electrode disposed in different layers, the oxide semiconductor is disposed between the first gate electrode and the second gate electrode, and the first gate electrode and the second gate electrode are connected to receive a common voltage signal.

公开(公告)号：US11869896B2

公开(公告)日：2024-01-09

申请号：US17368200

申请日：2021-07-06

Applicant: Samsung Display Co., Ltd.

Inventor： Woo Bin Lee ,  Seok Hwan Bang ,  Seung Sok Son ,  Woo Geun Lee ,  Soo Jung Chae

IPC: H01L27/12 ,  H10K59/121 ,  H10K77/10 ,  H10K102/00

CPC classification number: H01L27/1222 ,  H01L27/1218 ,  H01L27/1225 ,  H10K59/1213 ,  H10K77/111 ,  H10K2102/311

Abstract: A display device includes a substrate and a transistor disposed on the substrate and including a semiconductor layer, wherein the semiconductor layer includes a mesh structure, and wherein a plurality of openings are formed in the semiconductor layer.

公开(公告)号：US09893203B2

公开(公告)日：2018-02-13

申请号：US15246366

申请日：2016-08-24

Applicant: Samsung Display Co., Ltd.

Inventor： Seok Hwan Bang ,  Sook-Hwan Ban ,  Hyung Jun Kim ,  Woo Geun Lee ,  Hyeon Jun Lee

IPC: H01L29/786 ,  H01L27/12 ,  H01L27/32 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L29/7869 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/3248 ,  H01L27/3276 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/78696

Abstract: One or more exemplary embodiments disclose a thin film transistor array panel and a manufacturing method thereof including a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.