公开(公告)号：US12142690B2

公开(公告)日：2024-11-12

申请号：US18588163

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

公开(公告)号：US12040402B2

公开(公告)日：2024-07-16

申请号：US17690178

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang Xu ,  Nam Kyu Cho ,  Seok Hoon Kim ,  Yong Seung Kim ,  Pan Kwi Park ,  Dong Suk Shin ,  Sang Gil Lee ,  Si Hyung Lee

IPC: H01L29/76 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/7851 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791

Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.

公开(公告)号：US20240194789A1

公开(公告)日：2024-06-13

申请号：US18588163

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78618 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

公开(公告)号：US11990552B2

公开(公告)日：2024-05-21

申请号：US17533719

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryong Ha ,  Seok Hoon Kim ,  Jung Taek Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/78618 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78696 ,  H01L29/42392

Abstract: A semiconductor device includes an active pattern which includes a lower pattern, and a sheet pattern that is spaced apart from the lower pattern in a first direction, a gate structure on the lower pattern that includes a gate electrode that surrounds the sheet pattern, the gate electrode extending in a second direction that is perpendicular to the first direction, and a source/drain pattern on the lower pattern and in contact with the sheet pattern. A contact surface between the sheet pattern and the source/drain pattern has a first width in the second direction, and the sheet pattern has a second width in the second direction that is greater than the first width.

公开(公告)号：US20220190168A1

公开(公告)日：2022-06-16

申请号：US17519967

申请日：2021-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

公开(公告)号：US20220181500A1

公开(公告)日：2022-06-09

申请号：US17533719

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryong Ha ,  Seok Hoon Kim ,  Jung Taek Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes an active pattern which includes a lower pattern, and a sheet pattern that is spaced apart from the lower pattern in a first direction, a gate structure on the lower pattern that includes a gate electrode that surrounds the sheet pattern, the gate electrode extending in a second direction that is perpendicular to the first direction, and a source/drain pattern on the lower pattern and in contact with the sheet pattern. A contact surface between the sheet pattern and the source/drain pattern has a first width in the second direction, and the sheet pattern has a second width in the second direction that is greater than the first width.

公开(公告)号：US20180025901A1

公开(公告)日：2018-01-25

申请号：US15416408

申请日：2017-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum Seok Park ,  Sun Jung Kim ,  Yi Hwan Kim ,  Pan Kwi Park ,  Dong Suk Shin ,  Hyun Kwan Yu ,  Seung Hun Lee

IPC: H01L21/02 ,  B08B7/04 ,  H01L29/66 ,  B08B7/00 ,  H01L21/67 ,  H01L21/687

CPC classification number: H01L21/02057 ,  B08B7/0035 ,  B08B7/04 ,  H01J37/32091 ,  H01J37/32889 ,  H01J2237/335 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/67034 ,  H01L21/67109 ,  H01L21/67167 ,  H01L21/67184 ,  H01L21/67201 ,  H01L21/6831 ,  H01L21/68707 ,  H01L21/68742 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

Abstract: A precleaning apparatus includes a chamber having an internal space in which a substrate is cleaned, a substrate support disposed in the chamber and configured to support the substrate, a plasma generation unit disposed in the chamber and configured to generate plasma gas, a heating unit configured to heat the substrate on the substrate support, a cleaning gas supply unit configured to supply gas for oxide etching to the internal space of the chamber, and a hydrogen gas supply unit configured to supply hydrogen gas to the internal space of the chamber.