Method of forming an integrated circuit devices having buried word lines

    公开(公告)号:US12207456B2

    公开(公告)日:2025-01-21

    申请号:US18525187

    申请日:2023-11-30

    Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

    Light emitting device
    12.
    发明授权

    公开(公告)号:US11018276B2

    公开(公告)日:2021-05-25

    申请号:US16459859

    申请日:2019-07-02

    Abstract: A light emitting device includes a first pixel that includes a first light-emitting structure, a first color conversion layer on the first light-emitting structure, and a first multi-layered filter on the first color conversion layer, and a second pixel that includes a second light-emitting structure, a second color conversion layer on the second light-emitting structure, and a second multi-layered filter on the second color conversion layer. Each of the first and second multi-layered filters includes at least one stack including a first film and a second film. The first multi-layered filter outputs light of a wavelength band that is different from a wavelength band of light output from the second multi-layered filter. The first multi-layered filter reflects light not output back into the first pixel and the second multi-layered filter reflects light not output back into the second pixel.

    Electronic device including speaker module

    公开(公告)号:US12063471B2

    公开(公告)日:2024-08-13

    申请号:US18372983

    申请日:2023-09-26

    CPC classification number: H04R1/2811 H04R2499/11 H04R2499/15

    Abstract: According to an embodiment of the disclosure, an electronic device may include a housing including a first housing and a second housing receiving at least a portion of the first housing and configured to guide a slide of the first housing, a display including a first display area disposed on the second housing and a second display area extending from the first display area, a speaker module disposed in the housing, a resonance space facing at least a portion of the speaker module and configured to vary in size based on a slide of the first housing with respect to the second housing, and a processor configured to adjust a sound output from the speaker module based on the size of the resonance space.

    Integrated circuit devices having buried word lines therein

    公开(公告)号:US11889681B2

    公开(公告)日:2024-01-30

    申请号:US17720664

    申请日:2022-04-14

    CPC classification number: H10B12/34 H10B12/053 H10B12/315 H10B12/482

    Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

    Electronic device including speaker module

    公开(公告)号:US11805357B2

    公开(公告)日:2023-10-31

    申请号:US17501055

    申请日:2021-10-14

    CPC classification number: H04R1/2811 H04R2499/11 H04R2499/15

    Abstract: According to an embodiment of the disclosure, an electronic device may include a housing including a first housing and a second housing receiving at least a portion of the first housing and configured to guide a slide of the first housing, a display including a first display area disposed on the second housing and a second display area extending from the first display area, a speaker module disposed in the housing, a resonance space facing at least a portion of the speaker module and configured to vary in size based on a slide of the first housing with respect to the second housing, and a processor configured to adjust a sound output from the speaker module based on the size of the resonance space.

    Proximity correction methods for semiconductor manufacturing processes

    公开(公告)号:US11733603B2

    公开(公告)日:2023-08-22

    申请号:US17180984

    申请日:2021-02-22

    CPC classification number: G03F1/36 G03F7/70441 G03F7/70625 H01L21/027

    Abstract: A proximity correction method for a semiconductor manufacturing process includes: generating a plurality of pieces of original image data from a plurality of sample regions, with the sample regions selected from layout data used in the semiconductor manufacturing process; removing some pieces of original image data that overlap with each other from the plurality of pieces of original image data, resulting in a plurality of pieces of input image data; inputting the plurality of pieces of input image data to a machine learning model; obtaining a prediction value of critical dimensions of target patterns included in the plurality of pieces of input image data from the machine learning model; measuring a result value for critical dimensions of actual patterns corresponding to the target patterns on a semiconductor substrate on which the semiconductor manufacturing process is performed; and performing learning of the machine learning model using the prediction value and the result value.

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