公开(公告)号：US11244900B2

公开(公告)日：2022-02-08

申请号：US17029183

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggil Lee ,  Sukhoon Kim ,  Sungmyong Park ,  Chanyang Lee ,  Honyun Park

IPC: H01L23/528 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11573

Abstract: A wiring structure includes first to third metal patterns on a substrate. The first metal pattern extends in a second direction and has a first width in a third direction. The second metal pattern extends in the third direction to cross the first metal pattern and have a second width in the second direction. The third metal pattern is connected to the first and second metal patterns at an area where the first and second metal patterns cross each other, and has a substantially rectangular shape with concave portions in each quadrant. The third metal pattern has a third width defined as a minimum distance between opposite ones of the concave portions in a fourth direction having an acute angle to the second and third directions, which is less or equal to than a smaller of the first and second widths.

公开(公告)号：US12057323B2

公开(公告)日：2024-08-06

申请号：US17559766

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjine Park ,  Seohyun Kim ,  Sukhoon Kim ,  Jihoon Jeong ,  Younghoo Kim ,  Kuntack Lee

IPC: H01L21/3213 ,  G03F7/20 ,  G03F7/30 ,  G03F7/32 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/32139 ,  G03F7/2004 ,  G03F7/3021 ,  G03F7/325 ,  H01L21/308 ,  H01L21/31144

Abstract: A substrate processing method includes providing a surface tension reducing agent as a gas onto a substrate, the substrate having an exposed photoresist layer and layer of developer on the exposed photoresist layer, and causing a bulk flow of the developer in order to remove the developer from the substrate.

公开(公告)号：US20240120392A1

公开(公告)日：2024-04-11

申请号：US18244257

申请日：2023-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunjung Lee ,  Donggon Yoo ,  Jeongwon Hwang ,  Sukhoon Kim

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including active regions extending in a first direction; a device isolation layer surrounding the active regions on the substrate; gate structures intersecting the active regions and extending on the substrate in a second direction; source/drain regions on the active regions; contact plugs connected to the source/drain regions, respectively; a vertical buried structure penetrating through at least a portion of the device isolation layer, and in contact with the contact plugs; a vertical insulating layer covering at least a portion of side surfaces of the vertical buried structure; a horizontal buried structure below the vertical buried structure; a first conductive barrier covering at least a portion of an upper surface and side surfaces of the horizontal buried structure; and a metal-semiconductor compound pattern between the vertical buried structure and the first conductive barrier, wherein the vertical buried structure is between source/drain regions.

公开(公告)号：US20230232611A1

公开(公告)日：2023-07-20

申请号：US17892275

申请日：2022-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seran Oh ,  Sukhoon Kim ,  Sungjoo An ,  Yeonuk Kim

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10885

Abstract: A semiconductor device includes a substrate including a plurality of active patterns and a bit line intersecting at least one of the plurality of active patterns on the substrate and extending in a first direction. The bit line includes a first conductive pattern extending in the first direction, a bit line capping pattern extending in the first direction on the first conductive pattern, and a graphene pattern extending in the first direction between the first conductive pattern and the bit line capping pattern. The first conductive pattern may include ruthenium (Ru). The semiconductor device may also include one or more bit line contacts arranged in the first direction under the bit line, the one or more bit line contacts electrically connected to a respective one of the plurality of active patterns.

公开(公告)号：US11700722B2

公开(公告)日：2023-07-11

申请号：US17520868

申请日：2021-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewha Park ,  Moonkeun Kim ,  Sukhoon Kim ,  Dongchan Lim

IPC: H10B12/00

CPC classification number: H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor device manufacturing method according to the exemplary embodiments of the disclosure includes patterning a substrate, thereby forming an active pattern, forming a trench penetrating the active pattern, forming a support layer covering the trench, forming a first opening at the support layer, forming a gate electrode layer filling the trench through the first opening, and forming a bit line structure electrically connected to the active pattern. The support layer includes a base portion covering a top surface of the active pattern, and a support disposed in the trench.

公开(公告)号：US11535929B2

公开(公告)日：2022-12-27

申请号：US16898609

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Heon Park ,  Whankyun Kim ,  Sukhoon Kim ,  Junho Jeong

IPC: C23C14/46 ,  H01L21/687 ,  H01L21/67 ,  H01L21/677

Abstract: An ion beam deposition apparatus includes a substrate assembly to secure a substrate, a target assembly slanted with respect to the substrate assembly, the target assembly including a target with deposition materials, an ion gun to inject ion beams onto the target, such that ions of the deposition materials are discharged toward the substrate assembly to form a thin layer on the substrate, and a substrate heater to heat the substrate to a deposition temperature higher than a room temperature.

公开(公告)号：US20210225767A1

公开(公告)日：2021-07-22

申请号：US17029183

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggil Lee ,  Sukhoon Kim ,  Sungmyong Park ,  Chanyang Lee ,  Honyun Park

IPC: H01L23/528

Abstract: A wiring structure includes first to third metal patterns on a substrate. The first metal pattern extends in a second direction and has a first width in a third direction. The second metal pattern extends in the third direction to cross the first metal pattern and have a second width in the second direction. The third metal pattern is connected to the first and second metal patterns at an area where the first and second metal patterns cross each other, and has a substantially rectangular shape with concave portions in each quadrant. The third metal pattern has a third width defined as a minimum distance between opposite ones of the concave portions in a fourth direction having an acute angle to the second and third directions, which is less or equal to than a smaller of the first and second widths.