公开(公告)号：US20230232611A1

公开(公告)日：2023-07-20

申请号：US17892275

申请日：2022-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seran Oh ,  Sukhoon Kim ,  Sungjoo An ,  Yeonuk Kim

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10885

Abstract: A semiconductor device includes a substrate including a plurality of active patterns and a bit line intersecting at least one of the plurality of active patterns on the substrate and extending in a first direction. The bit line includes a first conductive pattern extending in the first direction, a bit line capping pattern extending in the first direction on the first conductive pattern, and a graphene pattern extending in the first direction between the first conductive pattern and the bit line capping pattern. The first conductive pattern may include ruthenium (Ru). The semiconductor device may also include one or more bit line contacts arranged in the first direction under the bit line, the one or more bit line contacts electrically connected to a respective one of the plurality of active patterns.

公开(公告)号：US12289880B2

公开(公告)日：2025-04-29

申请号：US17892275

申请日：2022-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seran Oh ,  Sukhoon Kim ,  Sungjoo An ,  Yeonuk Kim

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate including a plurality of active patterns and a bit line intersecting at least one of the plurality of active patterns on the substrate and extending in a first direction. The bit line includes a first conductive pattern extending in the first direction, a bit line capping pattern extending in the first direction on the first conductive pattern, and a graphene pattern extending in the first direction between the first conductive pattern and the bit line capping pattern. The first conductive pattern may include ruthenium (Ru). The semiconductor device may also include one or more bit line contacts arranged in the first direction under the bit line, the one or more bit line contacts electrically connected to a respective one of the plurality of active patterns.

公开(公告)号：US20250107073A1

公开(公告)日：2025-03-27

申请号：US18804605

申请日：2024-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seran Oh ,  Yunho Kang ,  Minsik Kim ,  Yeonuk Kim ,  Byounghoon Lee ,  Jangeun Lee

IPC: H10B12/00 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device may include a substrate including a first active region defined by a first device isolation layer, a bit line contact arranged on the first active region of the substrate, and a bit line that extends in a first direction on the substrate. The bit line includes a lower conductive layer arranged on the substrate and on a sidewall of the bit line contact and a metal line stack arranged on the lower conductive layer. The metal line stack includes a first conductive layer arranged on the lower conductive layer and the bit line contact and including a first metal material, a first intermediate layer arranged on the first conductive layer and including graphene, and a second conductive layer arranged on the first intermediate layer and including the first metal material.