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    Semiconductor device
    14.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11417656B2

    公开(公告)日：2022-08-16

    申请号：US16898719

    申请日：2020-06-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoon Tae Hwang ,  Sunjung Lee ,  Heonbok Lee ,  Geunwoo Kim ,  Wandon Kim

    IPC: H01L27/092 ,  H01L21/8238

    Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types from each other; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

    Methods of fabricating semiconductor devices including differing barrier layer structures
    15.
    发明授权
    Methods of fabricating semiconductor devices including differing barrier layer structures 有权

    公开(公告)号：US10804158B2

    公开(公告)日：2020-10-13

    申请号：US16785236

    申请日：2020-02-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Namgyu Cho ,  Kughwan Kim ,  Geunwoo Kim ,  Jungmin Park ,  Minwoo Song

    IPC: H01L21/82 ,  H01L29/40 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

    Abstract: A method of fabricating a semiconductor device may include forming a first conductive layer on first to third regions of a substrate, forming a barrier layer on the first conductive layer, the barrier layer including a first barrier layer, a second barrier layer, and a sacrificial layer which are sequentially formed, sequentially forming a second conductive layer and a third conductive layer on the barrier layer, performing a first etching process to remove the third conductive layer from the second region and the third region, the third conductive layer remaining on the first region after the first etching process, and performing a second etching process to remove the second conductive layer and the sacrificial layer from the third region, the second conductive layer and the sacrificial layer remaining on the first region and on the second region after the second etching process.

    Integrated circuit device
    16.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US12230682B2

    公开(公告)日：2025-02-18

    申请号：US17672033

    申请日：2022-02-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoontae Hwang ,  Geunwoo Kim ,  Wandon Kim ,  Hyunbae Lee

    IPC: H01L29/417 ,  H01L23/522 ,  H01L29/45

    Abstract: An integrated circuit (IC) device includes a conductive region including a first metal on a substrate. An insulating film is on the conductive region. A conductive plug including a second metal passes through the insulating film and extends in a vertical direction. A conductive barrier pattern is between the conductive region and the conductive plug. The conductive barrier pattern has a first surface in contact with the conductive region and a second surface in contact with the conductive plug. A bottom surface and a lower sidewall of the conductive plug are in contact with the conductive barrier pattern, and an upper sidewall of the conductive plug is in contact with the insulating film. The conductive barrier pattern includes a vertical barrier portion between the insulating film and the conductive plug, and the vertical barrier portion has a width tapering along a first direction away from the conductive region.

    Method of fabricating a semiconductor device
    17.
    发明授权
    Method of fabricating a semiconductor device 有权

    公开(公告)号：US11830874B2

    公开(公告)日：2023-11-28

    申请号：US17578982

    申请日：2022-01-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Geunwoo Kim ,  Yoon Tae Hwang ,  Wandon Kim ,  Hyunbae Lee

    IPC: H01L27/088 ,  H01L29/49 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L27/088 ,  H01L23/528 ,  H01L23/5226 ,  H01L29/4941

    Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

    Semiconductor device
    19.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11538916B2

    公开(公告)日：2022-12-27

    申请号：US17231126

    申请日：2021-04-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoontae Hwang ,  Wandon Kim ,  Geunwoo Kim ,  Heonbok Lee ,  Taegon Kim ,  Hanki Lee

    IPC: H01L29/45 ,  H01L29/78 ,  H01L29/417 ,  H01L23/532 ,  H01L23/485 ,  H01L23/522 ,  H01L29/66 ,  H01L21/285 ,  H01L29/08

    Abstract: A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

    Semiconductor package
    20.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11469188B2

    公开(公告)日：2022-10-11

    申请号：US17162444

    申请日：2021-01-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Geunwoo Kim

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538

    Abstract: A semiconductor package may include a package substrate, a molded interposer package (MIP) and a first stiffener. The MIP may be arranged on the package substrate. The MIP may include an interposer, at least one first semiconductor chip and at least one second semiconductor chip molded by a molding member. The first stiffener may be attached to any one of outer surfaces of the MIP. The first stiffener may be spaced apart from the upper surface of the package substrate to suppress a warpage of the MIP. Thus, central conductive bumps between the MIP and the package substrate may not be upwardly floated to improve an electrical connection between the central conductive bumps and the package substrate. Further, a short between edge conductive bumps between the MIP and the package substrate may not be generated.

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