公开(公告)号：US20240030286A1

公开(公告)日：2024-01-25

申请号：US18140905

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Heo ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Sumin Yu ,  Seojin Jeong ,  Edward Namkyu Cho ,  Ryong Ha

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66439

Abstract: An integrated circuit device includes a plurality of fin-type active areas extending in a first horizontal direction on a substrate, a plurality of channel regions respectively on the plurality of fin-type active areas, a plurality of gate lines surrounding the plurality of channel regions on the plurality of fin-type active areas and extending in a second horizontal direction that crosses the first horizontal direction, and a plurality of source/drain regions respectively at positions adjacent to the plurality of gate lines on the plurality of fin-type active areas and respectively in contact with the plurality of channel regions, and the plurality of source/drain regions respectively include a plurality of semiconductor layers and at least one air gap located therein.

公开(公告)号：US20230402459A1

公开(公告)日：2023-12-14

申请号：US18185941

申请日：2023-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seojin Jeong ,  Jungtaek Kim ,  Moonseung Yang ,  Sumin Yu ,  Edward Namkyu Cho ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L29/7851 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/42392

Abstract: An integrated circuit (IC) device includes a fin-type active region, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region, a source/drain region that is adjacent to the gate line on the fin-type active region and has a sidewall facing the channel region, wherein the source/drain region includes a first buffer layer, a second buffer layer, and a main body layer, which are sequentially stacked in a direction away from the fin-type active region, each include a Si1-xGex layer (x≠0) doped with a p-type dopant, and have different Ge concentrations, and the second buffer layer conformally covers a surface of the first buffer layer that faces the main body layer. A thickness ratio of the side buffer portion to the bottom buffer portion is in a range of about 0.9 to about 1.1.

公开(公告)号：US20220102498A1

公开(公告)日：2022-03-31

申请号：US17546690

申请日：2021-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhoon KIM ,  Dongmyoung Kim ,  Kanghun Moon ,  Hyunkwan Yu ,  Sanggil Lee ,  Seunghun Lee ,  Sihyung Lee ,  Choeun Lee ,  Edward Namkyu Cho ,  Yang Xu

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.

公开(公告)号：US20210028281A1

公开(公告)日：2021-01-28

申请号：US16806629

申请日：2020-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhoon Kim ,  Dongmyoung Kim ,  Kanghun Moon ,  Hyunkwan Yu ,  Sanggil Lee ,  Seunghun Lee ,  Sihyung Lee ,  Choeun Lee ,  Edward Namkyu Cho ,  Yang Xu

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.

公开(公告)号：US20200020774A1

公开(公告)日：2020-01-16

申请号：US16453347

申请日：2019-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cho-eun Lee ,  Seok-hoon Kim ,  Sang-gil Lee ,  Edward Namkyu Cho ,  Min-hee Choi ,  Seung-hun Lee

IPC: H01L29/08 ,  H01L29/78

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.

公开(公告)号：US09972701B2

公开(公告)日：2018-05-15

申请号：US15443160

申请日：2017-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-woo Kim ,  Hyun-jung Lee ,  Sun-jung Kim ,  Seung-hun Lee ,  Keum-seok Park ,  Edward Namkyu Cho

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/51 ,  H01L29/775 ,  H01L29/10

CPC classification number: H01L29/66742 ,  B82Y10/00 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1079 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/515 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a fin-type active area, nanosheets, a gate, a source/drain region, and insulating spacers. The fin-type active area protrudes from a substrate in a first direction. The nanosheets are spaced from an upper surface of the fin-type active area and include channel regions. The gate is over the fin-type active area. The source/drain region is connected to the nanosheets. The insulating spacers are in the fin-type active area and between the nanosheets. Air spaces are between the insulating spacers and the source/drain region based on positions of the insulating spacers.