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公开(公告)号：US20220238146A1
公开(公告)日：2022-07-28
申请号：US17483010
申请日：2021-09-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Byungsuk Woo , Changkyu Seol , Cheolmin Park , Sucheol Lee , Chanik Park
IPC: G11C7/22 , G11C7/16 , H01L25/065
Abstract: A high bandwidth memory system includes a motherboard; and a semiconductor package coupled to the motherboard. The semiconductor package includes a package substrate mounted on the motherboard and including signal lines providing a plurality of channels; a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit; and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange a data signal with each other through the plurality of channels, the data signal is a multilevel signal having M levels, where M is a natural number greater than 2, and the first PHY circuit compensates for distortion of the channels and performs digital signal processing to compensate for a mismatch between the channels.
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公开(公告)号：US11372551B2
公开(公告)日：2022-06-28
申请号：US16898935
申请日：2020-06-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byungyong Choi , Doohyun Kim , Changkyu Seol , Ilhan Park
Abstract: A method of operating a memory controller, the method including performing a state shaping operation on received data based on state shaping information in response to a write request, the received data and the write request being received from a host, the state shaping information representing a memory cell characteristic corresponding to a memory cell group on which the received data is to be programmed, and the state shaping information being received from a memory device, and transmitting transformation data to the memory device, the transformation data being generated through the state shaping operation.
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13.发明授权Semiconductor memory systems using regression analysis and read methods thereof 有权使用回归分析及其读取方法的半导体存储器系统公开(公告)号：US09552887B2
公开(公告)日：2017-01-24
申请号：US14811222
申请日：2015-07-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanghoon Kim , Jun Jin Kong , Changkyu Seol , Hong Rak Son
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3422 , G11C16/349
Abstract: A memory system includes: a bit counter and a regression analyzer. The bit counter is configured to generate a plurality of count values based on data read from selected memory cells using a plurality of different read voltages, each of the plurality of count values being indicative of a number of memory cells of a memory device having threshold voltages between pairs of the plurality of different read voltages. The regression analyzer is configured to determine read voltage for the selected memory cells based on the plurality of count values using regression analysis.
Abstract translation: 存储器系统包括：位计数器和回归分析器。 位计数器被配置为基于使用多个不同的读取电压从所选择的存储器单元读取的数据生成多个计数值，多个计数值中的每一个表示具有阈值电压的存储器件的存储单元的数量 在多个不同读取电压的对之间。 回归分析器被配置为使用回归分析来基于多个计数值来确定所选择的存储器单元的读取电压。
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公开(公告)号：US20240202067A1
公开(公告)日：2024-06-20
申请号：US18223124
申请日：2023-07-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seonghyeog CHOI , Changkyu Seol , Dong Kim , Inhoon Park , Jinsoo Lim , Youngdon Choi , Junghwan Choi
IPC: G06F11/10
CPC classification number: G06F11/10
Abstract: A method of operating a storage device includes: periodically performing a patrol read operation on a memory device; storing failure information according to the patrol read operation in a buffer memory; generating an uncorrectable error as a result of a first error correction operation performed on read data of the memory device; loading the failure information from the buffer memory; and performing a second error correction operation on the read data by using the failure information.
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公开(公告)号：US11757567B2
公开(公告)日：2023-09-12
申请号：US17590474
申请日：2022-02-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Changkyu Seol , Jiyoup Kim , Hyejeong So , Myoungbo Kwak , Pilsang Yoon , Sucheol Lee , Jinsoo Lim , Youngdon Choi
CPC classification number: H04L1/0041 , G06F1/03 , H04L1/0045 , H04L1/0057 , H04L1/0084
Abstract: Provided is a device and method for encoding and decoding to implement maximum transition avoidance coding with minimum overhead. An exemplary device performs encoding and/or decoding, by using sub-block lookup tables representing correlations between some bit values in a data burst and symbols, a combining lookup table selectively interconnecting the sub-block lookup tables based on remaining bit values of the data burst, and a codeword decoding lookup table designating the sub-block lookup tables corresponding to the symbols of each of received codewords.
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Patent Agency Ranking
公开(公告)号：US11631444B2
公开(公告)日：2023-04-18
申请号：US17483010
申请日：2021-09-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Byungsuk Woo , Changkyu Seol , Cheolmin Park , Sucheol Lee , Chanik Park
IPC: G11C7/22 , H01L25/065 , G11C7/16 , H01L27/108
Abstract: A high bandwidth memory system includes a motherboard; and a semiconductor package coupled to the motherboard. The semiconductor package includes a package substrate mounted on the motherboard and including signal lines providing a plurality of channels; a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit; and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange a data signal with each other through the plurality of channels, the data signal is a multilevel signal having M levels, where M is a natural number greater than 2, and the first PHY circuit compensates for distortion of the channels and performs digital signal processing to compensate for a mismatch between the channels.
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公开(公告)号：US11449274B2
公开(公告)日：2022-09-20
申请号：US17356687
申请日：2021-06-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Byungsuk Woo , Changkyu Seol , Sucheol Lee
IPC: G06F3/06
Abstract: A memory device includes: a memory cell array; a data selector configured to receive data from the memory cell array, and to output the received data as first sub-data and second sub-data; a cyclic redundancy check (CRC) generator configured to generate first CRC values corresponding to the first sub-data, and to generate second CRC values corresponding to the second sub-data; a CRC selector configured to determine an order of the first CRC values and the second CRC values, and to output one of the first CRC values and one of the second CRC values according to the determined order; and a transmitter configured to receive the first CRC values and the second CRC values according to the determined order, and to transmit CRC values of the data by a multilevel signaling method.
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公开(公告)号：US20220215865A1
公开(公告)日：2022-07-07
申请号：US17463635
申请日：2021-09-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byungsuk Woo , Sucheol Lee , Changkyu Seol
Abstract: A receiver that receives a multi-level signal includes a compensation circuit, a sampling circuit, an output circuit and a mode selector. The compensation circuit generates a plurality of data signals and a plurality of reference voltages by compensating intersymbol interference on an input data signal. The sampling circuit generates a plurality of sample signals based on the plurality of data signals and the plurality of reference voltages. The output circuit generates output data based on the plurality of sample signals, and selects a current value of the output data based on a previous value of the output data. The mode selector generates a mode selection signal used to select one of first and second operation modes based on an operating environment. The compensation circuit and the sampling circuit are entirely enabled in the first operation mode, and the compensation circuit and the sampling circuit are partially enabled in the second operation mode.
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公开(公告)号：US20210132832A1
公开(公告)日：2021-05-06
申请号：US16828170
申请日：2020-03-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyejeong So , Changkyu Seol , Hong Rak Son , Pilsang Yoon , Jinsoo Lim , Jae Hun Jang , Seonghyeong Choi
Abstract: A storage device is provided including a memory controller having a neural processing unit (NPU); a first nonvolatile memory (NVM) connected to the memory controller through a first channel; and a second NVM connected to the memory controller through a second channel. The first NVM stores first weight data for the NPU and the second stores second weight data for the NPU. The memory controller is configured to determine one of the first and second channels that is less frequently accessed upon receiving an inference request from the neural processor, and access a corresponding one of the first weight data and the second weight data using the determined one channel.
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公开(公告)号：US10459788B2
公开(公告)日：2019-10-29
申请号：US15676623
申请日：2017-08-14
Inventor： Donghwan Lee , Sae-Young Chung , Lanying Zhao , Sungik Choi , Junjin Kong , Changkyu Seol , Hyejeong So , Hong Rak Son
Abstract: A method of decoding may include performing fewer than ⌊ 2 k - 1 k ⌋ number of sensing operations of multilevel cells within a nonvolatile memory device, decoding pages corresponding to each of the sensing operations while correcting a channel error using an RIO code, and extracting user data from the decoded pages.
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