公开(公告)号：US20150179825A1

公开(公告)日：2015-06-25

申请号：US14332958

申请日：2014-07-16

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Kyu SUNG ,  Chang Su Jang ,  In-Hyuk Song ,  Kyu Hyun Mo ,  Sun Jae Yoon

IPC: H01L29/861 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/36 ,  H01L29/402 ,  H01L29/66136 ,  H01L29/8611

Abstract: A diode device may include a first conductivity type first semiconductor region, a second conductivity type second semiconductor region partially formed inside an upper portion of the first semiconductor region, and second conductivity type third semiconductor regions partially formed inside the upper portion of the first semiconductor region, formed on sides of the second semiconductor region, and having an impurity concentration higher than that of the second semiconductor region.

Abstract translation: 二极管器件可以包括第一导电类型的第一半导体区域，部分地形成在第一半导体区域的上部内的第二导电类型的第二半导体区域，以及部分地形成在第一半导体区域的上部内的第二导电类型的第三半导体区域 形成在第二半导体区域的侧面上，其杂质浓度高于第二半导体区域的杂质浓度。

公开(公告)号：US20140167150A1

公开(公告)日：2014-06-19

申请号：US13871082

申请日：2013-04-26

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kee Ju UM ,  In Hyuk Song ,  Chang Su Jang ,  Jaehoon Park ,  Dong Soo Seo

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66348

Abstract: There is provided a power semiconductor device including a contact formed in an active region, a trench gate extendedly formed from the first region into a first termination region and formed alternately with the contact, a first conductive well formed between the contact of the active region and the trench gate, a first conductive well extending portion formed in the first termination region and a part of a second termination region, and a first conductive field limiting ring formed in the second termination region and contacting the well extending portion.

Abstract translation: 提供了一种功率半导体器件，包括形成在有源区中的触点，从第一区延伸形成第一终端区并与触点交替形成的沟槽栅，形成在有源区的触点和 沟槽栅极，形成在第一端接区域中的第一导电阱延伸部分和第二端接区域的一部分，以及形成在第二端接区域中并接触阱延伸部分的第一导电场限制环。

公开(公告)号：US20140145291A1

公开(公告)日：2014-05-29

申请号：US13795858

申请日：2013-03-12

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk Song ,  Kee Ju Um ,  Chang Su Jang ,  Jae Hoon Park ,  Dong Soo Seo

IPC: H01L29/06

CPC classification number: H01L29/402 ,  H01L29/0619 ,  H01L29/41741 ,  H01L29/66348 ,  H01L29/7397

Abstract: Disclosed herein is a power semiconductor device. The power semiconductor device includes a second conductive type first junction termination extension (JTE) layer that is formed so as to be in contact with one side of the second conductive type well layer, a second conductive type second JTE layer that is formed on the same line as the second conductive type first JTE layer, and is formed so as to be spaced apart from the second conductive type first JTE layer in a length direction of the substrate, and a poly silicon layer that is formed so as to be in contact with the second conductive type well layer and an upper portion of the second conductive type first JTE layer.

Abstract translation: 这里公开了功率半导体器件。 功率半导体器件包括形成为与第二导电类型阱层的一侧接触的第二导电型第一结端接延伸（JTE）层，形成在其上的第二导电型第二JTE层 线作为第二导电型第一JTE层，并且形成为在基板的长度方向上与第二导电型第一JTE层间隔开，并且形成为与第二导电型第一JTE层接触的多晶硅层 第二导电类型阱层和第二导电型第一JTE层的上部。

公开(公告)号：US09502498B2

公开(公告)日：2016-11-22

申请号：US14617158

申请日：2015-02-09

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Kyu Hyun Mo ,  Dong Soo Seo ,  Chang Su Jang ,  Jae Hoon Park ,  In Hyuk Song

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/0634 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827

Abstract: A power semiconductor device may include a first conductivity type semiconductor substrate, a super-junction portion disposed on the first conductivity type semiconductor substrate and including a first conductivity type pillar and a second conductivity type pillar arranged in an alternating manner, and a three-dimensional (3D) gate portion disposed on the first conductivity type pillar. The 3D gate portion is disposed on the first conductivity type pillar to reduce the widths of the first and second conductivity type pillars, thereby effectively reducing a device size.

Abstract translation: 功率半导体器件可以包括第一导电类型半导体衬底，设置在第一导电类型半导体衬底上的超接合部分，并且包括交替排列的第一导电型柱和第二导电型柱，并且三维 （3D）门部分，设置在第一导电型柱上。 3D栅极部分设置在第一导电型柱上以减小第一和第二导电型柱的宽度，从而有效地减小了器件尺寸。

公开(公告)号：US09287363B2

公开(公告)日：2016-03-15

申请号：US14273269

申请日：2014-05-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon Park ,  In Hyuk Song ,  Chang Su Jang ,  Kee Ju Um

IPC: H01L29/16 ,  H01L21/04 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/1608 ,  H01L21/049 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device may include: preparing a substrate formed of SiC; depositing crystalline or amorphous silicon (Si) on one surface of the substrate to form a first semiconductor layer; and performing a heat treatment under a nitrogen atmosphere to form a second semiconductor layer formed of SiCN between the substrate and the first semiconductor layer.

Abstract translation: 制造半导体器件的方法可以包括：制备由SiC形成的衬底; 在所述衬底的一个表面上沉积晶体或非晶硅（Si）以形成第一半导体层; 并在氮气气氛下进行热处理，以在衬底和第一半导体层之间形成由SiCN形成的第二半导体层。

公开(公告)号：US09147757B2

公开(公告)日：2015-09-29

申请号：US13874038

申请日：2013-04-30

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kee Ju Um ,  Dong Soo Seo ,  Chang Su Jang ,  In Hyuk Song ,  Jaehoon Park

IPC: H01L29/74 ,  H01L29/739 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/7395 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/404 ,  H01L29/423 ,  H01L29/66333

Abstract: There is provided a power semiconductor device, including: a first conductive type drift layer, a second conductive type termination layer formed on an upper portion of an edge of the drift layer, and a high concentration first conductive type channel stop layer formed on a side surface of the edge of the drift layer.

Abstract translation: 提供了一种功率半导体器件，包括：第一导电型漂移层，形成在漂移层的边缘的上部上的第二导电型端接层和形成在侧面的高浓度第一导电型沟道阻挡层 漂移层边缘的表面。

公开(公告)号：US08981423B2

公开(公告)日：2015-03-17

申请号：US13937589

申请日：2013-07-09

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Dong Soo Seo ,  Jaehoon Park ,  Kee Ju Um ,  Chang Su Jang ,  In Hyuk Song

IPC: H01L29/66 ,  H01L29/739

CPC classification number: H01L29/7395 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/7397

Abstract: There is provided a power semiconductor device, including a plurality of trench gates formed to be spaced apart from each other by a predetermined distance, a current increasing part formed between the trench gates and including a first conductivity-type emitter layer and a gate oxide formed on a surface of the trench gate, and an immunity improving part formed between the trench gates and including a second conductivity-type body layer, a preventing film formed on the surface of the trench gate, and a gate oxide having a thickness less than that the gate oxide of the current increasing part.

Abstract translation: 提供了一种功率半导体器件，包括形成为彼此间隔开预定距离的多个沟槽栅极，形成在沟槽栅极之间并包括第一导电型发射极层和形成的栅极氧化物的电流增加部分 在所述沟槽栅极的表面上形成的抗扰度改善部以及形成在所述沟槽栅极之间并且包括第二导电型体层的抗扰度改善部，以及形成在所述沟槽栅极的表面上的防止膜和厚度小于所述沟槽栅极的厚度的栅极氧化物。 电流增加部分的栅极氧化物。

公开(公告)号：US20140312383A1

公开(公告)日：2014-10-23

申请号：US14322346

申请日：2014-07-02

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk SONG ,  Jae Hoon Park ,  Dong Soo Seo ,  Chang Su Jang

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L21/265 ,  H01L21/26513 ,  H01L29/36 ,  H01L29/66348

Abstract: A power semiconductor device may include: abase substrate including a first conductive type drift layer; a second conductive type semiconductor substrate disposed on the other surface of the base substrate; a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer; a second conductive type well layer disposed inside of one surface of the base substrate; a trench formed from one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction; a first insulation film disposed on a surface of the base substrate; and a first electrode disposed in the trench. A peak point of an impurity doping concentration of the diffusion layer in a transverse direction may be positioned in a region contacting a side surface of the trench.

Abstract translation: 功率半导体器件可以包括：包括第一导电型漂移层的基板; 设置在所述基底基板的另一个表面上的第二导电型半导体基板; 第一导电型扩散层，设置在所述基底衬底中，其杂质浓度高于所述漂移层的杂质浓度; 设置在所述基底基板的一个表面内的第二导电型阱层; 从包括所述阱层的所述基底基板的一个表面形成的沟槽，以在深度方向上穿过所述扩散层; 设置在所述基底基板的表面上的第一绝缘膜; 以及设置在沟槽中的第一电极。 扩散层在横向上的杂质掺杂浓度的峰值点可以位于与沟槽的侧表面接触的区域中。

公开(公告)号：US20140159105A1

公开(公告)日：2014-06-12

申请号：US13831780

申请日：2013-03-15

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kee Ju Um ,  In Hyuk Song ,  Chang Su Jang ,  Jae Hoon Park ,  Dong Soo Seo

IPC: H01L29/739

CPC classification number: H01L29/7397 ,  H01L29/1095 ,  H01L29/41741

Abstract: Disclosed herein is a power semiconductor device, including: a drift layer formed on the first surface of the semiconductor substrate, a well layer of a first conductive type, formed on the drift layer, a trench formed to reach the drift layer through the well layer, a first electrode formed in the trench, a second conductive type of second electrode region formed on the well layer, including a first region contacting the trench in a perpendicular direction and a second region spaced apart from the trench in a parallel direction and being perpendicular to the first region, a first conductive type of second electrode region formed to contact a side surface of the second conductive type of second electrode region, and a second electrode formed on the well layer and electrically connected to the second conductive type of second electrode region and the first conductive type of second electrode region.

Abstract translation: 本文公开了一种功率半导体器件，包括：形成在半导体衬底的第一表面上的漂移层，形成在漂移层上的第一导电类型的阱层，形成为通过阱层到达漂移层的沟槽 ，形成在沟槽中的第一电极，形成在阱层上的第二导电类型的第二电极区域，包括在垂直方向上接触沟槽的第一区域和在平行方向上与沟槽间隔开的第二区域，并且垂直 形成为与第二导电类型的第二电极区域的侧表面接触的第一导电类型的第二电极区域和形成在阱层上并与第二导电类型的第二电极区域电连接的第二电极 和第一导电类型的第二电极区域。