公开(公告)号：US20180340978A1

公开(公告)日：2018-11-29

申请号：US15916016

申请日：2018-03-08

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI ,  Shinji TANAKA

IPC: G01R31/3177 ,  G11C15/04 ,  G06F11/27

Abstract: An object of the present invention is to provide a highly-reliable content addressable memory. Provided is a content addressable memory including: a plurality of CAM cells; a word line joined to the CAM cells; a plurality of bit lines joined to the CAM cells; a plurality of search lines joined to the CAM cells; a match line joined to the CAM cells; a match amplifier joined to the match line; and a selection circuit that can select the output of the match amplifier in accordance with the value of the word line.

公开(公告)号：US20180315471A1

公开(公告)日：2018-11-01

申请号：US16030943

申请日：2018-07-10

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI ,  Shinji TANAKA

IPC: G11C11/417 ,  G11C5/04 ,  G11C5/14

CPC classification number: G11C11/417 ,  G11C5/04 ,  G11C5/148

Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided.The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal. Setting and cancelling of the second low power consumption mode, in which regions where a power source is shut down are different from those in the first low power consumption mode, of each memory module are sequentially performed according to the first control signal that is propagated through the propagation path.

公开(公告)号：US20170117060A1

公开(公告)日：2017-04-27

申请号：US15281947

申请日：2016-09-30

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Shunya NAGATA ,  Shinji TANAKA

IPC: G11C29/12 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C29/12 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C29/025 ,  G11C29/12015 ,  G11C29/18 ,  G11C2029/1202

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

公开(公告)号：US20160133315A1

公开(公告)日：2016-05-12

申请号：US14981195

申请日：2015-12-28

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA ,  Makoto YABUUCHI ,  Yuta YOSHIDA

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C11/418

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract translation: 提供了具有减小操作时序的变化的存储单元的半导体器件。 例如，半导体器件设置有与适当的位线相对布置的虚拟位线，以及顺序耦合到虚拟位线的列方向负载电路。 每个列方向负载电路设置有多个固定在截止状态的NMOS晶体管，其中预定的NMOS晶体管具有适当地耦合到任何虚拟位线的源极和漏极。 将与预定NMOS晶体管的扩散层电容相关的负载电容加到虚拟位线，并且对应于负载电容，建立从解码激活信号到虚拟位线信号的延迟时间。 当设置读出放大器的启动定时时，采用虚拟位线信号。

公开(公告)号：US20180342308A1

公开(公告)日：2018-11-29

申请号：US15947992

申请日：2018-04-09

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA

IPC: G11C29/20 ,  G01R31/3181 ,  G11C29/10 ,  G11C7/10

CPC classification number: G11C29/20 ,  G01R31/31813 ,  G11C7/1096 ,  G11C29/10 ,  G11C29/46

Abstract: A semiconductor device is comprised of a memory cell array with multiple memory cells arranged in a matrix, multiple bit-line pairs provided for each memory cell column in the memory cell array, multiple input/output circuits provided respectively corresponding to the multiple bit-line pairs, and as interface control circuit that controls the data input/output to the multiple input/output circuits when performing the data write and data read for each memory cell row in a normal mode. The interface control circuit is comprised of a selection circuit. When the data write and data read are performed for each memory cell row in a test mode, the selection circuit selects the data input/output to one of first input/output circuit and a second input/output circuit, respectively corresponding to a first memory cell included in the memory cell row and a second memory cell adjoining the first memory cell, according to a test address.

公开(公告)号：US20180158513A1

公开(公告)日：2018-06-07

申请号：US15812538

申请日：2017-11-14

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA ,  Makoto YABUUCHI

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419 ,  G11C11/417

CPC classification number: G11C11/418 ,  G11C5/145 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417 ,  G11C11/419

Abstract: The semiconductor device includes a supply circuit for supplying a boosted voltage to a distal end of a wiring driven by a drive signal. The supply circuit includes an inverter circuit having an input coupled to the wiring, and a switch element controlled by an output signal of the inverter circuit. The switch element couples the boosted voltage to the distal end of the wiring.

公开(公告)号：US20180047457A1

公开(公告)日：2018-02-15

申请号：US15782662

申请日：2017-10-12

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA ,  Yuichiro ISHII ,  Masaki TSUKUDE ,  Yoshikazu SAITO

IPC: G11C29/02 ,  G11C11/419 ,  G11C29/50 ,  G11C29/18 ,  G11C11/418 ,  G11C29/12 ,  G11C29/04 ,  G11C29/28

CPC classification number: G11C7/00 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/28 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form, the test method including writing first data into a plurality of memory cells, while a plurality of word lines disposed in the columns of the memory cells are deselected, driving the low-potential side bit line of a bit line pair in the selected column, which is among a plurality of bit line pairs disposed in the columns of the memory cells, to a negative voltage level in accordance with second data complementary to the first data, and reading the data written into the memory cells.

公开(公告)号：US20170092352A1

公开(公告)日：2017-03-30

申请号：US15373783

申请日：2016-12-09

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Ken SHIBATA ,  Shinji TANAKA ,  Makoto YABUUCHI ,  Noriaki MAEDA

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

公开(公告)号：US20150023091A1

公开(公告)日：2015-01-22

申请号：US14504994

申请日：2014-10-02

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Yoshikazu SAITO ,  Shinji TANAKA ,  Koji NII

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412 ,  G11C15/00 ,  G11C15/04

Abstract: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the read word line WLB corresponding to the selected memory cell 3. A write operation activates the write word line WLA corresponding to the selected memory cell 3. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.

Abstract translation: 半导体器件避免了干扰问题以及DP-SRAM单元或2P-SRAM单元中的写入和读取操作之间的冲突。 半导体器件1包括写入字线WLA和读取字线WLB，每个读取字线WLB都耦合到存储器单元3.读取操作激活对应于所选择的存储器单元3的读取字线WLB。写入操作激活相应的写入字线WLA 所选择的写入字线WLA在执行读取和写入操作的操作周期中激活所选择的读取字线WLB之后被激活。

公开(公告)号：US20240143281A1

公开(公告)日：2024-05-02

申请号：US18471683

申请日：2023-09-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji TANAKA ,  Daiki KITAGATA

IPC: G06F7/544

CPC classification number: G06F7/5443

Abstract: A related-art semiconductor device has a problem that is a large operation error. A semiconductor device according to an embodiment includes: an input control circuit dividing a plurality of bit values representing an input value into a plurality of division values each having a predetermined number of bits, and outputting the division values; a plurality of memory units each including a plurality of memory cells each outputting a product of a held value represented by a ternary value and any one of the plurality of bit values representing the input value, each of the plurality of memory units corresponding to any one of the division values; and a sum operation circuit performing sum operation processing to an output value to be output for each of the division values, and outputting a final operation result value.