公开(公告)号：US20130200472A1

公开(公告)日：2013-08-08

申请号：US13738217

申请日：2013-01-10

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L29/78 ,  H01L29/40

CPC classification number: H01L21/76895 ,  H01L21/76849 ,  H01L21/823885 ,  H01L23/49822 ,  H01L27/0688 ,  H01L27/10858 ,  H01L27/1104 ,  H01L27/11551 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.

Abstract translation: 提高了布置在多层布线层中的半导体元件的性能。 半导体器件包括：布置在第一布线层中的第一布线; 布置在层叠在第一布线层上的第二布线层中的第二布线; 栅电极，其在第一布线层和第二布线层的层叠方向上配置在第一布线和第二布线之间，不与第一布线和第二布线相连; 设置在所述栅电极的侧表面上的栅极绝缘膜; 以及通过栅极绝缘膜设置在栅电极的侧表面上并与第一线和第二线耦合的半导体层。

公开(公告)号：US20130168817A1

公开(公告)日：2013-07-04

申请号：US13670138

申请日：2012-11-06

Applicant: Renesas Electronics Corporation

Inventor： Jun KAWAHARA ,  Naoya INOUE ,  Naoya FURUTAKE ,  Yoshihiro HAYASHI

IPC: H01L49/02

CPC classification number: H01L28/24 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/0802 ,  H01L2924/0002 ,  Y10S257/904 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.

Abstract translation: 半导体器件包括：第一绝缘层（层间绝缘层），设置在第一绝缘层（层间绝缘层）上的电阻元件，至少其表面层为TaSiN层;以及层间绝缘层， 第一绝缘层（层间绝缘层）和电阻元件。 在层间绝缘层中设置多个具有与TaSiN层结合的端子的通孔塞。

公开(公告)号：US20150371945A1

公开(公告)日：2015-12-24

申请号：US14843549

申请日：2015-09-02

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro HIJIOKA ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L23/528 ,  H01L29/94 ,  H01L23/532 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10835 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L28/91 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact.

Abstract translation: 半导体器件包括衬底，层间绝缘层，第一晶体管，多层互连层，电容器件，金属互连和第一触点。 层间绝缘膜设置在基板上。 将第一晶体管设置在衬底上并埋在层间绝缘层中。 第一晶体管至少具有栅电极和扩散电极。 多层互连层设置在层间绝缘膜的上方。 电容器件设置在多层互连层中。 金属互连与栅电极的上表面接触并埋在层间绝缘层中。 第一触点耦合到第一晶体管的扩散层并且被埋在层间绝缘层中。 金属互连包括与第一接触相同的材料。

公开(公告)号：US20150214218A1

公开(公告)日：2015-07-30

申请号：US14679385

申请日：2015-04-06

Applicant: Renesas Electronics Corporation

Inventor： Kishou KANEKO ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L27/06

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012

Abstract: A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element circuit is provided with transistors formed using semiconductor layers formed over a diffusion insulating film formed above a semiconductor substrate. The active element circuit is controlled by the logic circuit.

Abstract translation: 半导体器件包括逻辑电路和有源元件电路。 逻辑电路设置有形成在半导体衬底中的半导体元件。 有源元件电路设置有使用在半导体衬底上形成的扩散绝缘膜上形成的半导体层形成的晶体管。 有源元件电路由逻辑电路控制。

公开(公告)号：US20140080228A1

公开(公告)日：2014-03-20

申请号：US14022565

申请日：2013-09-10

Applicant: Renesas Electronics Corporation

Inventor： Makoto UEKI ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L43/12

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/08

Abstract: A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.

Abstract translation: 一种半导体器件，其中MRAM形成在包含在多层布线层中的布线层A中，所述MRAM具有与形成在布线层中并彼此绝缘的第一布线接触的至少两个第一磁化闭塞层，自由磁化 层在平面图中与两个第一磁化钉扎层重叠，并与第一磁化钉扎层，位于自由磁化层上方的非磁性层和位于非磁性层上的第二磁化钉扎层连接。

公开(公告)号：US20130134418A1

公开(公告)日：2013-05-30

申请号：US13745291

申请日：2013-01-18

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro Hayashi ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L29/41

CPC classification number: H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

Abstract: A semiconductor device, includes a semiconductor substrate, a first interconnect layer formed over the semiconductor substrate, a gate electrode formed in the first interconnect layer, a gate insulating film formed over the gate electrode, a second interconnect layer formed over the gate insulating film, an oxide semiconductor layer formed in the second interconnect layer, and a via formed in the second interconnect layer and connected to the oxide semiconductor layer. The gate electrode, the gate insulating film and the oxide semiconductor layer overlap in a plan view.

Abstract translation: 一种半导体器件，包括半导体衬底，形成在半导体衬底上的第一互连层，形成在第一互连层中的栅电极，形成在栅电极上的栅极绝缘膜，形成在栅极绝缘膜上的第二互连层， 形成在第二互连层中的氧化物半导体层和形成在第二互连层中并连接到氧化物半导体层的通孔。 栅电极，栅极绝缘膜和氧化物半导体层在平面图中重叠。

公开(公告)号：US20160211173A1

公开(公告)日：2016-07-21

申请号：US15087427

申请日：2016-03-31

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro Hayashi ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

Abstract: The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.

Abstract translation: 一种制造半导体器件的方法，包括制备半导体衬底，在所述半导体衬底上形成第一绝缘层，在第一绝缘膜中形成第一沟槽，分别在第一沟槽中形成栅电极和第一互连，形成 在所述栅电极上形成栅绝缘膜，在所述栅绝缘上形成半导体层，在所述半导体层和所述第一绝缘膜上形成第二绝缘层，在所述第二绝缘层中形成通孔，以及形成第二互连， 互连通过通孔连接到半导体层。 栅电极，第一互连和第二互连分别由Cu或Cu合金形成。

公开(公告)号：US20160172354A1

公开(公告)日：2016-06-16

申请号：US14995706

申请日：2016-01-14

Applicant: Renesas Electronics Corporation

Inventor： Kishou KANEKO ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L27/02 ,  H01L29/24 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/0285 ,  H01L23/522 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is formed above the semiconductor substrate; a plurality of wiring lines which are embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer; and a drain electrode connected with the semiconductor layer. The plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer. The semiconductor layer, the source electrode, the drain electrode and the gate electrode configure an ESD protection device to discharge a current by ESD surge from the first pad to the second pad.

Abstract translation: 半导体器件包括其上形成半导体器件的半导体衬底; 第一和第二垫; 形成在半导体衬底上的第一绝缘膜; 埋设在第一绝缘膜中的沟槽中的多条布线; 设置为覆盖所述第一绝缘膜和所述多条布线的第二绝缘膜; 形成在所述第二绝缘膜上的半导体层; 与半导体层连接的源电极; 以及与半导体层连接的漏电极。 多个布线包括设置在与半导体层相对的位置的栅电极。 半导体层，源电极，漏电极和栅电极构成ESD保护器件，以通过ESD浪涌从第一焊盘向第二焊盘放电。

公开(公告)号：US20150287832A1

公开(公告)日：2015-10-08

申请号：US14744261

申请日：2015-06-19

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro Hayashi ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/49 ,  H01L29/24 ,  H01L27/12 ,  H01L29/792

CPC classification number: H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

Abstract: A semiconductor device including a semiconductor substrate, a first insulating layer formed over said semiconductor substrate, first grooves formed in said first insulating layer, a gate electrode and a first interconnect filled in said first grooves, respectively, a gate insulating film formed over said gate electrode, a semiconductor layer formed over said gate insulating, a second insulating layer formed over said semiconductor layer and said first insulating film, a via formed in said second insulating layer and connected to said semiconductor layer, a second groove formed in said second insulating layer, and a second interconnect filled in said second groove, formed over said via and connected to said via.

Abstract translation: 一种半导体器件，包括半导体衬底，形成在所述半导体衬底上的第一绝缘层，分别形成在所述第一绝缘层中的第一沟槽，栅电极和填充在所述第一沟槽中的第一互连，栅极绝缘膜分别形成在所述栅极 电极，形成在所述栅极绝缘上的半导体层，形成在所述半导体层和所述第一绝缘膜上的第二绝缘层，形成在所述第二绝缘层中并连接到所述半导体层的通孔，形成在所述第二绝缘层中的第二沟槽 以及填充在所述第二凹槽中的第二互连件，形成在所述通孔上并连接到所述通孔。

公开(公告)号：US20140357047A1

公开(公告)日：2014-12-04

申请号：US14458976

申请日：2014-08-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Jun KAWAHARA ,  Naoya INOUE ,  Naoya FURUTAKE ,  Yoshihiro HAYASHI

IPC: H01L49/02

CPC classification number: H01L28/24 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/0802 ,  H01L2924/0002 ,  Y10S257/904 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.

Abstract translation: 半导体器件包括：第一绝缘层（层间绝缘层），设置在第一绝缘层（层间绝缘层）上的电阻元件，至少其表面层为TaSiN层;以及层间绝缘层， 第一绝缘层（层间绝缘层）和电阻元件。 在层间绝缘层中设置多个具有与TaSiN层结合的端子的通孔塞。