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    Analog receiver front-end with variable gain amplifier embedded in an equalizer structure
    12.
    发明授权
    Analog receiver front-end with variable gain amplifier embedded in an equalizer structure 有权

    公开(公告)号：US11863356B2

    公开(公告)日：2024-01-02

    申请号：US17589782

    申请日：2022-01-31

    Applicant: QUALCOMM Incorporated

    Inventor： Miao Li ,  Zhiqin Chen ,  Yu Song ,  Hongmei Liao ,  Zhi Zhu ,  Hao Liu ,  Lejie Lu

    IPC: H04L25/03

    CPC classification number: H04L25/03057 ,  H04L25/03885

    Abstract: A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.

    High-speed sampler
    14.
    发明授权
    High-speed sampler 有权

    公开(公告)号：US11711077B1

    公开(公告)日：2023-07-25

    申请号：US17805211

    申请日：2022-06-02

    Applicant: QUALCOMM Incorporated

    Inventor： Chiu Keung Tang ,  Zhiqin Chen

    IPC: G11C7/06 ,  H03K17/687 ,  G11C27/02 ,  H03K19/20

    CPC classification number: H03K17/6872 ,  G11C7/06 ,  G11C27/02 ,  H03K17/6874 ,  H03K19/20

    Abstract: A regeneration circuit includes a first inverting circuit and a second inverting circuit. The regeneration circuit also includes a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit, a third transistor and a fourth transistor. A gate of the first transistor and a gate of the fourth transistor are coupled to a first input, and a gate of the second transistor and a gate of the fourth transistor are coupled to a second input. The regeneration circuit further includes a first switch and a second switch. The first switch and the third transistor are coupled in series between a first rail and the first transistor, and the second switch and the fourth transistor are coupled in series between the first rail and the second transistor.

    Efficient clock forwarding scheme
    15.
    发明授权
    Efficient clock forwarding scheme 有权

    公开(公告)号：US10698439B1

    公开(公告)日：2020-06-30

    申请号：US16413292

    申请日：2019-05-15

    Applicant: QUALCOMM Incorporated

    Inventor： Li Sun ,  Russell Deans ,  Zhiqin Chen ,  Zhi Zhu

    IPC: H04L7/00 ,  G06F1/08 ,  G06F1/06

    Abstract: In certain aspects, an apparatus includes a multiplexer having a first input, a second input, a select input, and an output, wherein the first input is configured to receive a first reference clock signal, the second input is configured to receive a second reference clock signal, and the select input is configured to receive a select signal. The multiplexer is configured to select one of the first and second reference clock signals based on the select signal, and output the selected one of the first and second reference clock signals at the output of the multiplexer. The apparatus also includes a clock driver having an input and an output, wherein the input of the clock driver is coupled to the output of the multiplexer.

    CIRCUIT FOR GENERATING ACCURATE CLOCK PHASE SIGNALS FOR HIGH-SPEED SERDES
    18.
    发明申请
    CIRCUIT FOR GENERATING ACCURATE CLOCK PHASE SIGNALS FOR HIGH-SPEED SERDES 有权
    用于生成高速SERDES的精确时钟相位信号的电路

    公开(公告)号：US20150303909A1

    公开(公告)日：2015-10-22

    申请号：US14257913

    申请日：2014-04-21

    Applicant: QUALCOMM Incorporated

    Inventor： Kenneth Arcudia ,  Zhiqin Chen

    IPC: H03K5/156 ,  H03M9/00 ,  H03L7/06

    CPC classification number: H03K5/1565 ,  H03L7/06 ,  H03L7/0807 ,  H03L7/0812 ,  H03M9/00

    Abstract: Systems and methods for generating clock phase signals with accurate timing relations are disclosed. For example, four clock signals spaced by 90 degrees can be generating from differential CML clock signals. A CML to CMOS converter converts the differential CML clock signals to differential CMOS clock signals and provides duty cycle correction. Delay cells produce delayed clock signals from the differential CMOS clock signals. The differential CMOS clock signals and the delayed clock signals are logically combined to produce four quarter clock signals having active times of one-quarter clock period. Set-reset latches produce the four clock signals from the quarter clock signals. A calibration module control delays of the delay cells and controls the duty cycle correction of the CML to CMOS converter to adjust the timing relationships of the four clock signals. The four clock signals may be used, for example, in a deserializer.

    Abstract translation: 公开了用于产生具有精确定时关系的时钟相位信号的系统和方法。 例如，可以从差分CML时钟信号产生间隔90度的四个时钟信号。 CML到CMOS转换器将差分CML时钟信号转换为差分CMOS时钟信号，并提供占空比校正。 延迟单元从差分CMOS时钟信号产生延迟的时钟信号。 差分CMOS时钟信号和延迟的时钟信号被逻辑地组合以产生具有四分之一时钟周期的有效时间的四分之四四个时钟信号。 设置复位锁存器从四分之一时钟信号产生四个时钟信号。 校准模块控制延迟单元的延迟，并控制CML到CMOS转换器的占空比校正，以调整四个时钟信号的时序关系。 四个时钟信号可以例如在解串器中使用。

    DELAY ARCHITECTURE FOR REDUCING DOWNTIME DURING FREQUENCY SWITCHING
    19.
    发明申请
    DELAY ARCHITECTURE FOR REDUCING DOWNTIME DURING FREQUENCY SWITCHING 审中-公开
    延迟架构在频率切换期间减少停机

    公开(公告)号：US20150109034A1

    公开(公告)日：2015-04-23

    申请号：US14056861

    申请日：2013-10-17

    Applicant: QUALCOMM INCORPORATED

    Inventor： Narasimhan Vasudevan ,  Zhiqin Chen ,  Li Pan ,  Michael Thomas Fertsch ,  Nan Chen

    IPC: H03L7/08

    CPC classification number: H03L7/0995 ,  G11C7/222 ,  H03L7/0805 ,  H03L7/0816

    Abstract: A delay architecture for reducing downtime during frequency switching is described herein. In one embodiment, an adjustable delay circuit comprises a phase-locked loop (PLL) or a delay-locked loop (DLL) configured to generate a bias voltage, and a plurality of delay elements coupled in series, wherein each of the delay elements is biased by the bias voltage. The adjustable delay circuit also comprises a multiplexer coupled to outputs of two or more of the delay elements, wherein each of the outputs corresponds to a different delay of an input signal, and wherein the multiplexer is configured to select one of the outputs based on a data frequency of a memory interface.

    Abstract translation: 这里描述了用于在频率切换期间减少停机时间的延迟架构。 在一个实施例中，可调延迟电路包括被配置为产生偏置电压的锁相环（PLL）或延迟锁定环（DLL）以及串联耦合的多个延迟元件，其中每个延迟元件是 由偏置电压偏置。 可调延迟电路还包括耦合到两个或更多个延迟元件的输出的多路复用器，其中每个输出对应于输入信号的不同延迟，并且其中多路复用器被配置为基于 存储器接口的数据频率。

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