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    Quadrature clock generation with injection locking
    13.
    发明授权
    Quadrature clock generation with injection locking 有权

    公开(公告)号：US10476434B1

    公开(公告)日：2019-11-12

    申请号：US15990311

    申请日：2018-05-25

    Applicant: QUALCOMM Incorporated

    Inventor： Bupesh Pandita ,  Zhuo Gao ,  Eskinder Hailu

    IPC: H03B5/00 ,  H03B5/06 ,  H03K3/03 ,  H04L7/06 ,  H04L27/16 ,  H03L7/18

    Abstract: Aspects of the disclosure are directed to quadrature clock generation with injection locking. In accordance with one aspect, quadrature clock generation with injection locking uses a digital calibration circuit having a coarse calibration circuit and a fine calibration circuit to perform a coarse frequency calibration of a controlled oscillator, wherein the controlled oscillator is coupled to the digital calibration circuit; characterize a replica oscillator signal path associated with an oscillator replica circuit, wherein the oscillator replica circuit is coupled to the controlled oscillator; perform a fine frequency calibration of the controlled oscillator by measuring a phase difference between the controlled oscillator and the oscillator replica circuit; and generate a calibrated set of quadrature clock signals after performing the fine frequency calibration of the controlled oscillator.

    Delay locked loop (DLL) employing pulse to digital converter (PDC) for calibration
    17.
    发明授权
    Delay locked loop (DLL) employing pulse to digital converter (PDC) for calibration 有权

    公开(公告)号：US09998126B1

    公开(公告)日：2018-06-12

    申请号：US15644426

    申请日：2017-07-07

    Applicant: QUALCOMM Incorporated

    Inventor： Eskinder Hailu ,  Bupesh Pandita

    IPC: H03L7/085 ,  G04F10/00

    CPC classification number: H03L7/085 ,  G04F10/00 ,  G04F10/005 ,  H03L7/0814

    Abstract: Aspects of the disclosure are directed to generating a quadrature clock signal from an in-phase clock signal. In accordance with one aspect, a delay locked loop (DLL), including a first pulse to digital converter (PDC) to generate a first pulse width measurement, wherein the first pulse width measurement includes a first sign and a first magnitude; a second pulse to digital converter (PDC) to generate a second pulse width measurement, wherein the second pulse width measurement includes a second sign and a second magnitude; a digital loop filter coupled to the first PDC and the second PDC, the digital loop filter to generate a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and a first delay generation block to generate a quadrature clock signal based on the filtered comparison output and an in-phase clock signal.

    NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE
    19.
    发明申请
    NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE 有权
    新的相位锁相环（PLL）架构

    公开(公告)号：US20170041005A1

    公开(公告)日：2017-02-09

    申请号：US14820894

    申请日：2015-08-07

    Applicant: QUALCOMM Incorporated

    Inventor： Bupesh Pandita ,  Hanan Cohen ,  Eskinder Hailu ,  Kenneth Luis Arcudia

    IPC: H03K21/10

    CPC classification number: H03K21/10 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1974 ,  H03L7/1976

    Abstract: In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.

    Abstract translation: 在一个实施例中，用于分频的方法包括将模数信号向上传播到一级级联分频器级从最后一级分频级到第一分频级，并且对于每个分频级，产生相应的本地 当模数信号传播到分频器级之后的负载信号。 该方法还包括对于每个分频器级，基于相应的本地负载信号将一个或多个相应的控制位输入到分频器级，所述一个或多个相应的控制位设置分频器级的分频器值。

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