公开(公告)号：US20200328350A1

公开(公告)日：2020-10-15

申请号：US16382880

申请日：2019-04-12

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Guoqing Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: An RRAM device is disclosed, having reduced area without increased performance variation, formed by employing a bounded filament formation region in which an oxide layer is thinner and an implanted ion concentration is higher than in a peripheral region of the oxide layer surrounding the bounded filament formation region. Filament formation is controlled to occur in a bounded region having a reduced area by thinning the oxide layer in the bounded region to increase an electric field strength in the bounded region. Defects in the bounded region are subject to greater force from the electric field than defects in the peripheral region. By implanting additional mobile ions or other ion species in the bounded region by an accurately controlled process, a higher concentration of defects is introduced into the bounded region to promote filament formation. Memory elements based on the RRAM device are formed at higher density and lower cost.

公开(公告)号：US10756085B2

公开(公告)日：2020-08-25

申请号：US15835810

申请日：2017-12-08

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Bin Yang ,  Lixin Ge

IPC: H01L27/088 ,  H01L27/06 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/762 ,  H03K19/0185 ,  H01L21/8234 ,  G06F30/398 ,  H01L27/092

Abstract: An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.

公开(公告)号：US20200235098A1

公开(公告)日：2020-07-23

申请号：US16255008

申请日：2019-01-23

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L27/092 ,  H01L29/24 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L27/02 ,  H01L21/8238

Abstract: Vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits are disclosed. A horizontal footprint of a CFET cell circuit may be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type channel structures. The N-type and P-type channel structures may be formed of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis andY-axis dimensions of the horizontal footprint are reduced.

公开(公告)号：US10714582B2

公开(公告)日：2020-07-14

申请号：US16002459

申请日：2018-06-07

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Ye Lu ,  Lixin Ge

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  G11C11/22 ,  H01L29/423 ,  H01L29/49

Abstract: A Field-Effect Transistor (FET) with a negative capacitance layer to increase power density provides a negative capacitor connected in series with a conventional positive capacitor. The dimensions of the negative capacitor are controlled to allow the difference in capacitances between the negative capacitor and the positive capacitor to approach zero, which in turn provides a large total capacitance. The large total capacitance provides for increased power density.

公开(公告)号：US10665678B2

公开(公告)日：2020-05-26

申请号：US16288558

申请日：2019-02-28

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Junjing Bao ,  Bin Yang ,  Lixin Ge ,  Yun Yue

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/72

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

公开(公告)号：US20190288662A1

公开(公告)日：2019-09-19

申请号：US15922013

申请日：2018-03-15

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao ,  Periannan Chidambaram

IPC: H03H9/02 ,  H03H9/72 ,  H03H9/13 ,  H03H9/145 ,  H03H9/64

Abstract: A surface acoustic wave (SAW) device comprises a substrate and composite electrodes. The composite electrodes comprise a metal layer and a graphene layer. The SAW device may be used to satisfy requirements for the fifth generation (5G) mobile communication.

公开(公告)号：US20190195700A1

公开(公告)日：2019-06-27

申请号：US16268669

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  Periannan Chidambaram ,  Bin Yang ,  Jiefeng Jeff Lin ,  Giridhar Nallapati ,  Bo Yu ,  Jie Deng ,  Jun Yuan ,  Stanley Seungchul Song

IPC: G01K7/01 ,  H01L23/522 ,  H01L23/34 ,  G01K7/18 ,  H01L49/02 ,  G01K7/24 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/528 ,  H01L21/66

CPC classification number: G01K7/01 ,  G01K7/186 ,  G01K7/24 ,  H01L21/32139 ,  H01L21/76895 ,  H01L22/34 ,  H01L23/34 ,  H01L23/5228 ,  H01L23/528 ,  H01L27/0629 ,  H01L28/24

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

公开(公告)号：US10263080B2

公开(公告)日：2019-04-16

申请号：US15672017

申请日：2017-08-08

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Junjing Bao ,  Bin Yang ,  Lixin Ge ,  Yun Yue

IPC: H01L29/66 ,  H01L29/16 ,  H01L21/02 ,  H01L29/10 ,  H01L29/72 ,  H01L29/78

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

公开(公告)号：US20190088660A1

公开(公告)日：2019-03-21

申请号：US15708913

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: H01L27/11 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/165 ,  H01L29/16 ,  H01L21/762 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  G11C11/419

Abstract: Bi-stable static random access memory (SRAM) bit cells that facilitate direct writing for storage are disclosed. In one aspect, a bi-stable SRAM bit cell includes source and drain regions, and a gate region formed over a well region between the source and drain regions, which results in two (2) bipolar junction transistors (BJTs) formed within a bi-stable SRAM bit cell. A base tap region and a collector tap region are employed to provide voltages for read and write operations. The base tap region is formed beside a shallow trench isolation (STI) region having a bottom surface higher in a Y-axis direction in the well region than a bottom surface of the well region. The collector tap region is formed on one side of an STI region having a bottom surface lower in the Y-axis direction in the substrate than the bottom surface of the well region.

公开(公告)号：US10205018B1

公开(公告)日：2019-02-12

申请号：US15676494

申请日：2017-08-14

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L27/092 ,  H01L21/8238

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device. The semiconductor device generally includes a substrate, a channel disposed above the substrate, and a first dielectric layer disposed adjacent to a first side of the channel. The semiconductor device may also include a first non-insulative region disposed between the first dielectric layer and the substrate, and a second dielectric layer disposed adjacent to a second side of the channel, wherein the first dielectric layer and the second dielectric layer comprise high-k layers. In certain aspects, a second non-insulative region may be disposed above the second dielectric layer, and a third non-insulative region may be disposed adjacent to a third side of the channel.