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11.发明授权Non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction 有权具有第一磁性隧道结和第二磁性隧道结的位单元处的不可逆状态公开(公告)号：US08797792B2
公开(公告)日：2014-08-05
申请号：US14022364
申请日：2013-09-10
Applicant: QUALCOMM Incorporated
Inventor： Hari M. Rao , Jung Pil Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
CPC classification number: G11C11/16 , G11C11/14 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C29/027
Abstract: A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.
Abstract translation: 存储器件包括磁性隧道结（MTJ）位单元。 MTJ位单元包括第一MTJ和第二MTJ。 存储器件还包括编程电路，其被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个来在位单元处产生不可逆状态。 不可逆状态对应于通过比较在第一MTJ读取的第一值和在第二MTJ读取的第二值确定的MTJ比特单元的值。
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公开(公告)号：US20140139209A1
公开(公告)日：2014-05-22
申请号：US13680432
申请日：2012-11-19
Applicant: QUALCOMM INCORPORATED
Inventor： Kangho Lee , Xiao Lu , Wah Nam Hsu , Seung H. Kang
IPC: G01R33/02
CPC classification number: G01R33/02 , G11C11/16 , G11C29/56016
Abstract: Several novel features pertain to an automatic testing equipment (ATE) memory tester that includes a load board, a projected-field electromagnet, a positioning mechanism and a memory tester. The load board is for coupling to a die package that includes a magnetoresistive random access memory (MRAM) having several cells, where each cell includes a magnetic tunnel junction (MTJ). The projected-field electromagnet is for applying a portion of a magnetic field across the MRAM. The portion of the magnetic field may be substantially uniform. The positioning mechanism is coupled to the electromagnet and the load board, and is configured to position the electromagnet vertically about (above/below) the die package when the die package is coupled to the load board. The memory tester is coupled to the load board. The memory tester is for testing the MRAM when the substantially uniform portion of the magnetic field is applied across the MRAM.
Abstract translation: 一些新颖的功能涉及自动测试设备（ATE）存储器测试器，其包括负载板，投射场电磁体，定位机构和存储器测试器。 负载板用于耦合到包括具有几个电池的磁阻随机存取存储器（MRAM）的管芯封装，其中每个电池包括磁性隧道结（MTJ）。 投射场电磁铁用于在MRAM上施加磁场的一部分。 磁场的部分可以是基本均匀的。 定位机构联接到电磁体和负载板，并且被配置为当模具封装耦合到负载板时，将电磁铁垂直地围绕模具封装（上/下）定位。 存储器测试器耦合到负载板。 当磁场的基本上均匀的部分被施加在MRAM上时，存储器测试器用于测试MRAM。
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13.发明申请NON-REVERSIBLE STATE AT A BITCELL HAVING A FIRST MAGNETIC TUNNEL JUNCTION AND A SECOND MAGNETIC TUNNEL JUNCTION 有权在具有第一磁性隧道连接和第二磁性隧道接头的位置处的不可逆状态公开(公告)号：US20140010006A1
公开(公告)日：2014-01-09
申请号：US14022364
申请日：2013-09-10
Applicant: QUALCOMM Incorporated
Inventor： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Taehyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew M. Nowak , Steven M. Millendorf , Asaf Ashkenazi
IPC: G11C11/14
CPC classification number: G11C11/16 , G11C11/14 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C29/027
Abstract: A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.
Abstract translation: 存储器件包括磁性隧道结（MTJ）位单元。 MTJ位单元包括第一MTJ和第二MTJ。 存储器件还包括编程电路，其被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个来在位单元处产生不可逆状态。 不可逆状态对应于通过比较在第一MTJ读取的第一值和在第二MTJ读取的第二值确定的MTJ比特单元的值。
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公开(公告)号：US20190066746A1
公开(公告)日：2019-02-28
申请号：US15688212
申请日：2017-08-28
Applicant: QUALCOMM Incorporated
Inventor： Xia Li , Wei-Chuan Chen , Wah Nam Hsu , Seung Hyuk Kang
Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.
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公开(公告)号：US10210920B1
公开(公告)日：2019-02-19
申请号：US15937317
申请日：2018-03-27
Applicant: QUALCOMM Incorporated
Inventor： Wei-Chuan Chen , Xia Li , Wah Nam Hsu , Seung Hyuk Kang
Abstract: Magnetic tunnel junction (MTJ) devices with varied breakdown voltages in different memory arrays fabricated in a same semiconductor die to facilitate different memory applications are disclosed. In exemplary aspects disclosed herein, MTJ devices are fabricated in a semiconductor die to provide at least two different memory arrays. MTJ devices in each memory array are fabricated to have different breakdown voltages. For example, it may be desired to fabricate a One-Time-Programmable (OTP) memory array in the semiconductor die using MTJ devices having a first, lower breakdown voltage, and a separate magneto-resistive random access memory (MRAM) in a same semiconductor die with MTJ devices having a higher breakdown voltage. Thus, in this example, lower breakdown voltage MTJ devices in OTP memory array require less voltage to program, while higher breakdown voltage MTJ devices in MRAM can maintain a desired write operation margin to avoid or reduce write operations causing dielectric breakdown.
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Patent Agency Ranking
公开(公告)号：US20170178741A1
公开(公告)日：2017-06-22
申请号：US15450055
申请日：2017-03-06
Applicant: QUALCOMM Incorporated
Inventor： Jung Pill Kim , Taehyun Kim , Kangho Lee , Seung H. Kang , Xia Li , Wah Nam Hsu
CPC classification number: G11C17/18 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C17/165
Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.
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17.发明申请MAGNETIC AUTOMATIC TEST EQUIPMENT (ATE) MEMORY TESTER DEVICE AND METHOD EMPLOYING TEMPERATURE CONTROL 有权磁性自动测试设备（ATE）存储器测试设备和采用温度控制的方法公开(公告)号：US20140254251A1
公开(公告)日：2014-09-11
申请号：US13787938
申请日：2013-03-07
Applicant: QUALCOMM INCORPORATED
Inventor： Kangho Lee , Wah Nam Hsu , Xiao Lu , Seung H. Kang
IPC: G11C29/04
CPC classification number: G11C29/04 , G11C7/04 , G11C11/16 , G11C29/00 , G11C29/56016
Abstract: In a particular embodiment, a method includes controlling a temperature within a chamber while applying a magnetic field. A device including a memory array is located in the chamber. The method includes applying a magnetic field to the memory array and testing the memory array during application of the magnetic field to the memory array at a target temperature.
Abstract translation: 在特定实施例中，一种方法包括在施加磁场的同时控制室内的温度。 包括存储器阵列的装置位于腔室中。 该方法包括在存储器阵列中施加磁场并在目标温度下将磁场施加到存储器阵列期间测试存储器阵列。
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公开(公告)号：US10534047B2
公开(公告)日：2020-01-14
申请号：US15474339
申请日：2017-03-30
Applicant: QUALCOMM Incorporated
Inventor： Wei-Chuan Chen , Wah Nam Hsu , Xia Li , Seung Hyuk Kang , Nicholas Ka Ming Stevens-Yu
Abstract: Tunnel magneto-resistive (TMR) sensors employing TMR devices with different magnetic field sensitivities for increased detection sensitivity are disclosed. For example, a TMR sensor may be used as a biosensor to detect the presence of biological materials. In aspects disclosed herein, free layers of at least two TMR devices in a TMR sensor are fabricated to exhibit different magnetic properties from each other (e.g., MR ratio, magnetic anisotropy, coercivity) so that each TMR device will exhibit a different change in resistance to a given magnetic stray field for increased magnetic field detection sensitivity. For example, the TMR devices may be fabricated to exhibit different magnetic properties such that one TMR device exhibits a greater change in resistance in the presence of a smaller magnetic stray field, and another TMR device exhibits a greater change in resistance in the presence of a larger magnetic stray field.
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公开(公告)号：US20190147930A1
公开(公告)日：2019-05-16
申请号：US16247247
申请日：2019-01-14
Applicant: QUALCOMM Incorporated
Inventor： Xia Li , Wei-Chuan Chen , Wah Nam Hsu , Seung Hyuk Kang
Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.
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公开(公告)号：US20180259581A1
公开(公告)日：2018-09-13
申请号：US15455253
申请日：2017-03-10
Applicant: QUALCOMM Incorporated
Inventor： Xia Li , Wei-Chuan Chen , Wah Nam Hsu , Yang Du
IPC: G01R31/3185 , H01L21/66 , H01L27/06 , H01L23/528 , H01L23/34 , H03K3/03 , H03K17/14
CPC classification number: G01R31/318513 , G01R31/318505 , H01L22/34 , H01L23/34 , H01L23/5286 , H01L25/0657 , H01L27/0688 , H03K3/0315 , H03K17/14
Abstract: Dynamically controlling voltage provided to three-dimensional (3D) integrated circuits (ICs) (3DICs) to account for process variations measured across interconnected IC tiers of 3DICs are disclosed herein. In one aspect, a 3DIC process variation measurement circuit (PVMC) is provided to measure process variation. The 3DIC PVMC includes stacked logic PVMCs configured to measure process variations of devices across multiple IC tiers and process variations of vias that interconnect multiple IC tiers. The 3DIC PVMC may include IC tier logic PVMCs configured to measure process variations of devices on corresponding IC tiers. These measured process variations can be used to dynamically control supply voltage provided to the 3DIC such that operation of the 3DIC approaches a desired process corner. Adjusting supply voltage using the 3DIC PVMC takes into account interconnected properties of the 3DIC such that the supply voltage is adjusted to cause the 3DIC to operate in the desired process corner.
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