公开(公告)号：US20180165789A1

公开(公告)日：2018-06-14

申请号：US15377801

申请日：2016-12-13

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Serag GadelRab ,  Zhenbiao Ma ,  Meghal Varia ,  Tao Wang ,  Tom Longo ,  Mark Sternberg ,  Paul Chow

IPC: G06T1/60 ,  G06T1/20 ,  G09G5/395 ,  G06T11/00

CPC classification number: G06T11/001 ,  G06T1/20 ,  G06T11/40 ,  G09G5/363 ,  G09G5/395 ,  G09G2340/02 ,  G09G2340/16 ,  G09G2350/00 ,  G09G2360/121 ,  G09G2360/122 ,  G09G2360/18

Abstract: Techniques are described in which a device is configured to retrieve a metadata buffer for rendering a sub-frame of a set of sub-frames for a frame. A data block of a data buffer is configured to store image data for rendering the sub-frame. In response to determining, based on the metadata buffer for rendering the sub-frame, that the sub-frame includes a color pattern, fixed color value, or combination thereof, the device refrains from retrieving the image data from the data block of the data buffer and determines the image data for rendering the sub-frame based on the metadata buffer.

公开(公告)号：US09824458B2

公开(公告)日：2017-11-21

申请号：US14862532

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Shambhoo Khandelwal ,  Yang Xia ,  Xuefeng Tang ,  Jian Liang ,  Tao Wang ,  Andrew Evan Gruber ,  Eric Demers

IPC: G06T7/20 ,  G06T1/60 ,  G06T1/20 ,  G06T15/80 ,  G06T15/00

CPC classification number: G06T7/20 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/80 ,  G06T2200/04 ,  G06T2200/28

Abstract: A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.

公开(公告)号：US20160232645A1

公开(公告)日：2016-08-11

申请号：US14618463

申请日：2015-02-10

Applicant: QUALCOMM Incorporated

Inventor： Tao Wang

IPC: G06T1/60 ,  G06T15/80 ,  G06T15/04 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F9/50 ,  G06T1/20 ,  G06T15/005 ,  G06T15/04 ,  G06T15/80 ,  G06T2200/28 ,  G06T2210/08

Abstract: This disclosure presents techniques and structures for graphics processing. In one example, a method of graphics processing may include rendering, with a graphics processing unit (GPU), one or more portions of a frame using one or more graphics operations, and writing, with the GPU, color data directly to a color buffer in a system memory in accordance with the one or more graphics operations. The method may further include writing, with the GPU, depth data to a depth buffer in a graphics memory in accordance with the one or more graphics operations, and resolving, with the GPU, the depth buffer in the graphics memory to the system memory when the rendering of the one or more portions of the frame is complete.

Abstract translation: 本公开提供用于图形处理的技术和结构。 在一个示例中，图形处理的方法可以包括使用图形处理单元（GPU），使用一个或多个图形操作来渲染帧的一个或多个部分，并且将GPU与彩色数据直接写入颜色缓冲器 在根据一个或多个图形操作的系统存储器中。 该方法还可以包括根据一个或多个图形操作将GPU深度数据写入图形存储器中的深度缓冲器，并且在GPU中将图形存储器中的深度缓冲器解析为系统存储器，当 帧的一个或多个部分的呈现完成。

公开(公告)号：US09245496B2

公开(公告)日：2016-01-26

申请号：US13725393

申请日：2012-12-21

Applicant: QUALCOMM Incorporated

Inventor： Andrew E. Gruber ,  Tao Wang ,  Shambhoo Khandelwal

IPC: G09G5/39 ,  G09G5/36 ,  G06F12/06 ,  G09G5/393 ,  G09G5/395 ,  G06F12/08

CPC classification number: G09G5/363 ,  G06F12/0607 ,  G06F12/0875 ,  G06F2212/1021 ,  G06F2212/455 ,  G06F2212/601 ,  G09G5/393 ,  G09G5/395

Abstract: This disclosure describes techniques for performing memory transfer operations with a graphics processing unit (GPU) based on a selectable memory transfer mode, and techniques for selecting a memory transfer mode for performing all or part of a memory transfer operation with a GPU. In some examples, the techniques of this disclosure may include selecting a memory transfer mode for performing at least part of a memory transfer operation, and performing, with a GPU, the memory transfer operation based on the selected memory transfer mode. The memory transfer mode may be selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode. The techniques of this disclosure may be used to improve the performance of GPU-assisted memory transfer operations.

Abstract translation: 本公开描述了基于可选存储器传输模式的用于执行图形处理单元（GPU）的存储器传送操作的技术，以及用于选择用于执行与GPU的存储器传送操作的全部或部分的存储器传送模式的技术。 在一些示例中，本公开的技术可以包括选择用于执行存储器传送操作的至少一部分的存储器传送模式，以及基于所选择的存储器传输模式使用GPU执行存储器传送操作。 可以从包括交织存储器传送模式和顺序存储器传输模式的至少两个不同的存储器传输模式的集合中选择存储器传送模式。 本公开的技术可以用于改善GPU辅助的存储器传送操作的性能。

公开(公告)号：US20140176586A1

公开(公告)日：2014-06-26

申请号：US13725393

申请日：2012-12-21

Applicant: QUALCOMM INCORPORATED

Inventor： Andrew E. Gruber ,  Tao Wang ,  Shambhoo Khandelwal

IPC: G09G5/36

CPC classification number: G09G5/363 ,  G06F12/0607 ,  G06F12/0875 ,  G06F2212/1021 ,  G06F2212/455 ,  G06F2212/601 ,  G09G5/393 ,  G09G5/395

Abstract: This disclosure describes techniques for performing memory transfer operations with a graphics processing unit (GPU) based on a selectable memory transfer mode, and techniques for selecting a memory transfer mode for performing all or part of a memory transfer operation with a GPU. In some examples, the techniques of this disclosure may include selecting a memory transfer mode for performing at least part of a memory transfer operation, and performing, with a GPU, the memory transfer operation based on the selected memory transfer mode. The memory transfer mode may be selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode. The techniques of this disclosure may be used to improve the performance of GPU-assisted memory transfer operations.

Abstract translation: 本公开描述了基于可选存储器传输模式的用于执行图形处理单元（GPU）的存储器传送操作的技术，以及用于选择用于执行与GPU的存储器传送操作的全部或部分的存储器传送模式的技术。 在一些示例中，本公开的技术可以包括选择用于执行存储器传送操作的至少一部分的存储器传送模式，以及基于所选择的存储器传输模式，使用GPU执行存储器传送操作。 可以从包括交织存储器传送模式和顺序存储器传输模式的至少两个不同的存储器传输模式的集合中选择存储器传送模式。 本公开的技术可以用于改善GPU辅助的存储器传送操作的性能。

公开(公告)号：US20240078735A1

公开(公告)日：2024-03-07

申请号：US18067837

申请日：2022-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jian Liang ,  Andrew Evan Gruber ,  Tao Wang ,  Xuefeng Tang ,  Vishwanath Shashikant Nikam ,  Nigel Poole ,  Kalyan Kumar Bhiravabhatla ,  Fei Xu ,  Zilin Ying

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.

公开(公告)号：US11893654B2

公开(公告)日：2024-02-06

申请号：US17373704

申请日：2021-07-12

Applicant: QUALCOMM Incorporated

Inventor： Sreyas Kurumanghat ,  Kalyan Kumar Bhiravabhatla ,  Andrew Evan Gruber ,  Tao Wang ,  Baoguang Yang ,  Pavan Kumar Akkaraju

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/40

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/405

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may configure a portion of a GPU to include at least one depth processing block, the at least one depth processing block being associated with at least one depth buffer. The apparatus may also identify one or more depth passes of each of a plurality of graphics workloads, the plurality of graphics workloads being associated with a plurality of frames. Further, the apparatus may process each of the one or more depth passes in the portion of the GPU including the at least one depth processing block, each of the one or more depth passes being processed by the at least one depth processing block, the one or more depth passes being associated with the at least one depth buffer.

公开(公告)号：US20180189179A1

公开(公告)日：2018-07-05

申请号：US15423889

申请日：2017-02-03

Applicant: QUALCOMM Incorporated

Inventor： Yun Li ,  Jian Liang ,  Fei Xu ,  Zhen Chen ,  Chun Yu ,  Tao Wang

IPC: G06F12/0811 ,  G06F12/0875 ,  G06F12/0846

CPC classification number: G06F12/0811 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/455

Abstract: A cache memory may receive, from a client, a request for a long cache line of data. The cache memory may receive, from a memory, the requested long cache line of data. The cache memory may store the requested long cache line of data into a plurality of data stores across a plurality of memory banks as a plurality of short cache lines of data distributed across the plurality of data stores in the cache memory. The cache memory may also store a plurality of tags associated with the plurality of short cache lines of data into one of a plurality of tag stores in the plurality of memory banks.

公开(公告)号：US20170352182A1

公开(公告)日：2017-12-07

申请号：US15174110

申请日：2016-06-06

Applicant: QUALCOMM Incorporated

Inventor： Tao Wang ,  Xuefeng Tang ,  Jian Liang

IPC: G06T15/30 ,  G06T15/40 ,  G06T15/00

CPC classification number: G06T15/30 ,  G06T1/20 ,  G06T15/005 ,  G06T15/40 ,  G06T15/405

Abstract: A graphics processing unit (GPU) may perform a binning pass to determine primitive-tile intersections for a plurality of primitives and a plurality of tiles making up a graphical scene, including performing low-resolution z-culling of representations of the plurality of primitives based at least in part on a first set of culling z-values each having a first test size to determine a first set of visible primitives from the plurality of primitives. The GPU may further perform a rendering pass to render the plurality of tiles based at least in part on performing the low-resolution z-culling of representations of the first set of visible primitives based at least in part on a second set of culling z-values that represents a second test size to determine a second set of visible primitives from the first set of visible primitives, wherein the first test size is greater than the second test size.

公开(公告)号：US09626762B2

公开(公告)日：2017-04-18

申请号：US14686696

申请日：2015-04-14

Applicant: QUALCOMM Incorporated

Inventor： Chunhui Mei ,  Tao Wang ,  Young In Yeo ,  Vineet Goel

IPC: G06T15/80 ,  G06T7/00 ,  G06T1/20 ,  G06T1/60 ,  G06T13/80 ,  G06T15/00 ,  G06T7/70

CPC classification number: G06T7/70 ,  G06T1/20 ,  G06T1/60 ,  G06T13/80 ,  G06T15/005 ,  G06T15/80 ,  G06T2210/12

Abstract: Techniques are described for stochastic rasterization. A graphics processing unit (GPU) may discard samples of bounding polygons that together indicate movement of one or more primitives before a pixel shader process the samples. The GPU may leverage a stencil buffer and stencil test for discarding of such samples.