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公开(公告)号：US20170084043A1
公开(公告)日：2017-03-23
申请号：US14862532
申请日：2015-09-23
Applicant: QUALCOMM Incorporated
Inventor： Shambhoo Khandelwal , Yang Xia , Xuefeng Tang , Jian Liang , Tao Wang , Andrew Evan Gruber , Eric Demers
CPC classification number: G06T7/20 , G06T1/20 , G06T1/60 , G06T15/005 , G06T15/80 , G06T2200/04 , G06T2200/28
Abstract: A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.
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2.发明授权Selectively merging partially-covered tiles to perform hierarchical z-culling 有权选择性地合并部分覆盖的瓦片来执行分层z剔除公开(公告)号：US09311743B2
公开(公告)日：2016-04-12
申请号：US14061506
申请日：2013-10-23
Applicant: QUALCOMM Incorporated
Inventor： Tao Wang , Andrew Evan Gruber , Shambhoo Khandelwal
CPC classification number: G06T15/405 , G06T1/60 , G06T15/005
Abstract: This disclosure describes techniques for performing hierarchical z-culling in a graphics processing system. In some examples, the techniques for performing hierarchical z-culling may involve selectively merging partially-covered source tiles for a tile location into a fully-covered merged source tile based on whether conservative farthest z-values for the partially-covered source tiles are nearer than a culling z-value for the tile location, and using a conservative farthest z-value associated with the fully-covered merged source tile to update the culling z-value for the tile location. In further examples, the techniques for performing hierarchical z-culling may use a cache unit that is not associated with an underlying memory to store conservative farthest z-values and coverage masks for merged source tiles. The capacity of the cache unit may be smaller than the size of cache needed to store merged source tile data for all of the tile locations in a render target.
Abstract translation: 本公开描述了在图形处理系统中执行分层z剔除的技术。 在一些示例中，用于执行分层z剔除的技术可以包括基于对于部分覆盖的源平铺的保守最远的z值是否更接近而选择性地将用于瓦片位置的部分覆盖的源瓦片合并到完全覆盖的合并源瓦片中 比用于瓦片位置的剔除z值，以及使用与完全覆盖的合并源平铺相关联的保守最远的z值来更新瓦片位置的剔除z值。 在另外的示例中，用于执行分层z剔除的技术可以使用与底层存储器不相关联的高速缓存单元来存储用于合并的源瓦片的保守最远的z值和覆盖掩码。 高速缓存单元的容量可以小于存储渲染目标中的所有瓦片位置的合并的源瓦片数据所需的高速缓存的大小。
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3.发明申请公开(公告)号：US20150109293A1
公开(公告)日：2015-04-23
申请号：US14061506
申请日：2013-10-23
Applicant: QUALCOMM Incorporated
Inventor： Tao Wang , Andrew Evan Gruber , Shambhoo Khandelwal
CPC classification number: G06T15/405 , G06T1/60 , G06T15/005
Abstract: This disclosure describes techniques for performing hierarchical z-culling in a graphics processing system. In some examples, the techniques for performing hierarchical z-culling may involve selectively merging partially-covered source tiles for a tile location into a fully-covered merged source tile based on whether conservative farthest z-values for the partially-covered source tiles are nearer than a culling z-value for the tile location, and using a conservative farthest z-value associated with the fully-covered merged source tile to update the culling z-value for the tile location. In further examples, the techniques for performing hierarchical z-culling may use a cache unit that is not associated with an underlying memory to store conservative farthest z-values and coverage masks for merged source tiles. The capacity of the cache unit may be smaller than the size of cache needed to store merged source tile data for all of the tile locations in a render target.
Abstract translation: 本公开描述了在图形处理系统中执行分层z剔除的技术。 在一些示例中，用于执行分层z剔除的技术可以包括基于对于部分覆盖的源平铺的保守最远的z值是否更接近而选择性地将用于瓦片位置的部分覆盖的源瓦片合并到完全覆盖的合并源瓦片中 比用于瓦片位置的剔除z值，以及使用与完全覆盖的合并源平铺相关联的保守最远的z值来更新瓦片位置的剔除z值。 在另外的示例中，用于执行分层z剔除的技术可以使用与底层存储器不相关联的高速缓存单元来存储用于合并的源瓦片的保守最远的z值和覆盖掩码。 高速缓存单元的容量可以小于存储渲染目标中的所有瓦片位置的合并的源瓦片数据所需的高速缓存的大小。
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公开(公告)号：US11373267B2
公开(公告)日：2022-06-28
申请号：US16673564
申请日：2019-11-04
Applicant: QUALCOMM Incorporated
Inventor： Tao Wang , Shambhoo Khandelwal , Andrew Evan Gruber , Shangmei Yu , Jing Gao , Junmei Shao , Thomas Edwin Frisinger , Rick Hammerstone
Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.
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Patent Agency Ranking
公开(公告)号：US20170083997A1
公开(公告)日：2017-03-23
申请号：US14857303
申请日：2015-09-17
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Rexford Alan Hill , Shambhoo Khandelwal
IPC: G06T1/60
CPC classification number: G06T1/60 , G06F12/0207 , G06F2212/401 , G06T1/20 , G06T11/40 , G06T2210/08
Abstract: A computing device may allocate a plurality of blocks in the memory, wherein each of the plurality of blocks is of a uniform fixed size in the memory. The computing device may further store a plurality of bandwidth-compressed graphics data into the respective plurality of blocks in the memory, wherein one or more of the plurality of bandwidth-compressed graphics data each has a size that is smaller than the fixed size. The computing device may further store data associated with the plurality of bandwidth-compressed graphics data into unused space of one or more of the plurality of blocks that contains the respective one or more of the plurality of bandwidth-compressed graphics data.
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公开(公告)号：US20200273142A1
公开(公告)日：2020-08-27
申请号：US16282003
申请日：2019-02-21
Applicant: QUALCOMM Incorporated
Inventor： Shambhoo Khandelwal , Tao Wang , Shangmei Yu , Jing Gao , Jian Liang , Andrew Evan Gruber , Chun Yu
Abstract: The described techniques provide for bin-based rendering where the scene geometry in a frame is subdivided into bins or tiles, and bins are resolved concurrently with the rendering of a next bin. For example, a graphics processing unit (GPU) may process an entire image and sort transactions (e.g., rasterized primitives, such as triangles) into bins. For the rendering of each transaction, a device may identify a memory address of a memory block (e.g., a unit or portion of internal GPU memory (GMEM)) the transaction will be written (i.e., rendered) to. The device may thus prepare the memory block for rendering (e.g., by performing a resolve operation, a clear operation, or an unresolve operation on the memory block), such that the memory block is prepared prior to rendering of the particular transaction. As such, transactions of a bin may be resolved concurrently with rendering of transactions of a next bin.
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公开(公告)号：US09824458B2
公开(公告)日：2017-11-21
申请号：US14862532
申请日：2015-09-23
Applicant: QUALCOMM Incorporated
Inventor： Shambhoo Khandelwal , Yang Xia , Xuefeng Tang , Jian Liang , Tao Wang , Andrew Evan Gruber , Eric Demers
CPC classification number: G06T7/20 , G06T1/20 , G06T1/60 , G06T15/005 , G06T15/80 , G06T2200/04 , G06T2200/28
Abstract: A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.
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8.发明授权Multi-mode memory access techniques for performing graphics processing unit-based memory transfer operations 有权用于执行图形处理单元的存储器传送操作的多模式存储器存取技术公开(公告)号：US09245496B2
公开(公告)日：2016-01-26
申请号：US13725393
申请日：2012-12-21
Applicant: QUALCOMM Incorporated
Inventor： Andrew E. Gruber , Tao Wang , Shambhoo Khandelwal
CPC classification number: G09G5/363 , G06F12/0607 , G06F12/0875 , G06F2212/1021 , G06F2212/455 , G06F2212/601 , G09G5/393 , G09G5/395
Abstract: This disclosure describes techniques for performing memory transfer operations with a graphics processing unit (GPU) based on a selectable memory transfer mode, and techniques for selecting a memory transfer mode for performing all or part of a memory transfer operation with a GPU. In some examples, the techniques of this disclosure may include selecting a memory transfer mode for performing at least part of a memory transfer operation, and performing, with a GPU, the memory transfer operation based on the selected memory transfer mode. The memory transfer mode may be selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode. The techniques of this disclosure may be used to improve the performance of GPU-assisted memory transfer operations.
Abstract translation: 本公开描述了基于可选存储器传输模式的用于执行图形处理单元（GPU）的存储器传送操作的技术，以及用于选择用于执行与GPU的存储器传送操作的全部或部分的存储器传送模式的技术。 在一些示例中，本公开的技术可以包括选择用于执行存储器传送操作的至少一部分的存储器传送模式，以及基于所选择的存储器传输模式使用GPU执行存储器传送操作。 可以从包括交织存储器传送模式和顺序存储器传输模式的至少两个不同的存储器传输模式的集合中选择存储器传送模式。 本公开的技术可以用于改善GPU辅助的存储器传送操作的性能。
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9.发明申请MULTI-MODE MEMORY ACCESS TECHNIQUES FOR PERFORMING GRAPHICS PROCESSING UNIT-BASED MEMORY TRANSFER OPERATIONS 有权用于执行图形处理的多模式存储器访问技术基于单元的存储器传输操作公开(公告)号：US20140176586A1
公开(公告)日：2014-06-26
申请号：US13725393
申请日：2012-12-21
Applicant: QUALCOMM INCORPORATED
Inventor： Andrew E. Gruber , Tao Wang , Shambhoo Khandelwal
IPC: G09G5/36
CPC classification number: G09G5/363 , G06F12/0607 , G06F12/0875 , G06F2212/1021 , G06F2212/455 , G06F2212/601 , G09G5/393 , G09G5/395
Abstract: This disclosure describes techniques for performing memory transfer operations with a graphics processing unit (GPU) based on a selectable memory transfer mode, and techniques for selecting a memory transfer mode for performing all or part of a memory transfer operation with a GPU. In some examples, the techniques of this disclosure may include selecting a memory transfer mode for performing at least part of a memory transfer operation, and performing, with a GPU, the memory transfer operation based on the selected memory transfer mode. The memory transfer mode may be selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode. The techniques of this disclosure may be used to improve the performance of GPU-assisted memory transfer operations.
Abstract translation: 本公开描述了基于可选存储器传输模式的用于执行图形处理单元（GPU）的存储器传送操作的技术，以及用于选择用于执行与GPU的存储器传送操作的全部或部分的存储器传送模式的技术。 在一些示例中，本公开的技术可以包括选择用于执行存储器传送操作的至少一部分的存储器传送模式，以及基于所选择的存储器传输模式，使用GPU执行存储器传送操作。 可以从包括交织存储器传送模式和顺序存储器传输模式的至少两个不同的存储器传输模式的集合中选择存储器传送模式。 本公开的技术可以用于改善GPU辅助的存储器传送操作的性能。
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