公开(公告)号：US11373267B2

公开(公告)日：2022-06-28

申请号：US16673564

申请日：2019-11-04

Applicant: QUALCOMM Incorporated

Inventor： Tao Wang ,  Shambhoo Khandelwal ,  Andrew Evan Gruber ,  Shangmei Yu ,  Jing Gao ,  Junmei Shao ,  Thomas Edwin Frisinger ,  Rick Hammerstone

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/393

Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.

公开(公告)号：US20200273142A1

公开(公告)日：2020-08-27

申请号：US16282003

申请日：2019-02-21

Applicant: QUALCOMM Incorporated

Inventor： Shambhoo Khandelwal ,  Tao Wang ,  Shangmei Yu ,  Jing Gao ,  Jian Liang ,  Andrew Evan Gruber ,  Chun Yu

IPC: G06T1/60 ,  G06F3/06

Abstract: The described techniques provide for bin-based rendering where the scene geometry in a frame is subdivided into bins or tiles, and bins are resolved concurrently with the rendering of a next bin. For example, a graphics processing unit (GPU) may process an entire image and sort transactions (e.g., rasterized primitives, such as triangles) into bins. For the rendering of each transaction, a device may identify a memory address of a memory block (e.g., a unit or portion of internal GPU memory (GMEM)) the transaction will be written (i.e., rendered) to. The device may thus prepare the memory block for rendering (e.g., by performing a resolve operation, a clear operation, or an unresolve operation on the memory block), such that the memory block is prepared prior to rendering of the particular transaction. As such, transactions of a bin may be resolved concurrently with rendering of transactions of a next bin.