公开(公告)号：US20210183005A1

公开(公告)日：2021-06-17

申请号：US16714052

申请日：2019-12-13

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Andrew Evan Gruber ,  Chihong Zhang ,  Gang Zhong ,  Jian Jiang ,  Fei Wei ,  Minjie Huang ,  Zilin Ying ,  Yang Xia ,  Jing Han ,  Chun Yu ,  Eric Demers

IPC: G06T1/20 ,  G06F9/38 ,  G06F9/50 ,  G06F9/30 ,  G06F1/03

Abstract: Methods, systems, and devices for graphic processing are described. The methods, systems, and devices may include or be associated with identifying a graphics instruction, determining that the graphics instruction is alias enabled for the device, partitioning an alias lookup table into one or more slots, allocating a slot of the alias lookup table based on the partitioning and determining that the graphics instruction is alias enabled, generating an alias instruction based on allocating the slot of the alias lookup table and determining that the graphics instruction is alias enabled, and processing the alias instruction.

公开(公告)号：US11954758B2

公开(公告)日：2024-04-09

申请号：US17652478

申请日：2022-02-24

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Andrew Evan Gruber ,  Zilin Ying ,  Chunling Hu ,  Baoguang Yang ,  Yang Xia ,  Gang Zhong ,  Chun Yu ,  Eric Demers

IPC: G06T1/20 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F9/505

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for dynamic wave pairing. A graphics processor may allocate one or more GPU workloads to one or more wave slots of a plurality of wave slots. The graphics processor may select a first execution slot of a plurality of execution slots for executing the one or more GPU workloads. The selection may be based on one of a plurality of granularities. The graphics processor may execute, at the selected first execution slot, the one or more GPU workloads at the one of the plurality of granularities.

公开(公告)号：US11204765B1

公开(公告)日：2021-12-21

申请号：US17003600

申请日：2020-08-26

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Fei Wei ,  Gang Zhong ,  Minjie Huang ,  Jian Jiang ,  Zilin Ying ,  Baoguang Yang ,  Yang Xia ,  Jing Han ,  Liangxiao Hu ,  Chihong Zhang ,  Chun Yu ,  Andrew Evan Gruber ,  Eric Demers

IPC: G06F9/30 ,  G06F9/38 ,  G06T1/20 ,  G06F9/50

Abstract: A graphics processing unit (GPU) utilizes block general purpose registers (bGPRs) to load multiple waves of samples for an instruction group into a processing pipeline and receive processed samples from the pipeline. The GPU acquires a credit for the bGPR for execution of the instruction group for a first wave using a persistent GPR and the bGPR. The GPU refunds the credit upon loading the first wave into the pipeline. The GPU executes a subsequent wave for the instruction group to load samples to the pipeline when at least one credit is available and the pipeline is processing the first wave. The GPU stores an indication of each wave that has been loaded into the pipeline in a queue. The GPU returns samples for a next wave in the queue from the pipeline to the bGPR for further processing when the physical slot of the bGPR is available.

公开(公告)号：US11132760B2

公开(公告)日：2021-09-28

申请号：US16714052

申请日：2019-12-13

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Andrew Evan Gruber ,  Chihong Zhang ,  Gang Zhong ,  Jian Jiang ,  Fei Wei ,  Minjie Huang ,  Zilin Ying ,  Yang Xia ,  Jing Han ,  Chun Yu ,  Eric Demers

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/50 ,  G06F9/38 ,  G06F1/03

Abstract: Methods, systems, and devices for graphic processing are described. The methods, systems, and devices may include or be associated with identifying a graphics instruction, determining that the graphics instruction is alias enabled for the device, partitioning an alias lookup table into one or more slots, allocating a slot of the alias lookup table based on the partitioning and determining that the graphics instruction is alias enabled, generating an alias instruction based on allocating the slot of the alias lookup table and determining that the graphics instruction is alias enabled, and processing the alias instruction.

公开(公告)号：US20170084043A1

公开(公告)日：2017-03-23

申请号：US14862532

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Shambhoo Khandelwal ,  Yang Xia ,  Xuefeng Tang ,  Jian Liang ,  Tao Wang ,  Andrew Evan Gruber ,  Eric Demers

IPC: G06T7/20 ,  G06T1/20 ,  G06T15/80 ,  G06T1/60

CPC classification number: G06T7/20 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/80 ,  G06T2200/04 ,  G06T2200/28

Abstract: A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.

公开(公告)号：US09824458B2

公开(公告)日：2017-11-21

申请号：US14862532

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Shambhoo Khandelwal ,  Yang Xia ,  Xuefeng Tang ,  Jian Liang ,  Tao Wang ,  Andrew Evan Gruber ,  Eric Demers

IPC: G06T7/20 ,  G06T1/60 ,  G06T1/20 ,  G06T15/80 ,  G06T15/00

CPC classification number: G06T7/20 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/80 ,  G06T2200/04 ,  G06T2200/28

Abstract: A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.

公开(公告)号：US11657471B2

公开(公告)日：2023-05-23

申请号：US17356434

申请日：2021-06-23

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Andrew Evan Gruber ,  Chihong Zhang ,  Jian Jiang ,  Gang Zhong ,  Baoguang Yang ,  Yang Xia ,  Chun Yu ,  Eric Demers

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may generate a table including a plurality of entries to store data associated with at least one of a constant value or an immediate value. The apparatus may also process, upon generating the table, first data including at least one of a constant value or an immediate value. Further, the apparatus may store, in the generated table, at least one of the constant value or the immediate value of the first data. The apparatus may also transmit, upon storing at least one of the constant value or the immediate value in the table, the table including the stored at least one of the constant value or the immediate value of the first data.